We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable name to what we real use to avoid confuse people.
Signed-off-by: YouMin Chen cym@rock-chips.com Signed-off-by: Kever Yang kever.yang@rock-chips.com ---
Changes in v2: None
arch/arm/mach-rockchip/sdram.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 8e5a572dba..af00a6b637 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -83,60 +83,60 @@ size_t rockchip_sdram_size(phys_addr_t reg) u32 cs1_col = 0; u32 bg = 0; u32 dbw, dram_type; - u32 sys_reg = readl(reg); + u32 sys_reg2 = readl(reg); u32 sys_reg3 = readl(reg + 4); - u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) + u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
- dram_type = (sys_reg >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; - debug("%s %x %x\n", __func__, (u32)reg, sys_reg); + dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; + debug("%s %x %x\n", __func__, (u32)reg, sys_reg2); for (ch = 0; ch < ch_num; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK); - cs0_col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & + cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); cs1_col = cs0_col; - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) == 0x2) { cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) & SYS_REG_CS1_COL_MASK); if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & - SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg >> + SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK) == 7) cs0_row = 12; else - cs0_row = 13 + (sys_reg >> + cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK) + ((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & SYS_REG_EXTEND_CS0_ROW_MASK) << 2); if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) & - SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg >> + SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK) == 7) cs1_row = 12; else - cs1_row = 13 + (sys_reg >> + cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK) + ((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) & SYS_REG_EXTEND_CS1_ROW_MASK) << 2); } else { - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK); } - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; if (dram_type == DDR4) { - dbw = (sys_reg >> SYS_REG_DBW_SHIFT(ch)) & + dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK; bg = (dbw == 2) ? 2 : 1; }