From: Stephen Warren swarren@nvidia.com
Rather than building a large table of all possible PLLX configurations into U-Boot and having it select the right one at run-time, push the configuration into SoC-specific files, and have the linker pick up the correct one.
Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/mach-tegra/cpu.c | 124 +--------------------------------- arch/arm/mach-tegra/cpu.h | 7 -- arch/arm/mach-tegra/pllx.h | 20 ++++++ arch/arm/mach-tegra/tegra114/Makefile | 3 +- arch/arm/mach-tegra/tegra114/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra124/Makefile | 3 +- arch/arm/mach-tegra/tegra124/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra20/Makefile | 1 + arch/arm/mach-tegra/tegra20/pllx.c | 59 ++++++++++++++++ arch/arm/mach-tegra/tegra210/Makefile | 3 +- arch/arm/mach-tegra/tegra210/pllx.c | 33 +++++++++ arch/arm/mach-tegra/tegra30/Makefile | 3 +- arch/arm/mach-tegra/tegra30/pllx.c | 34 ++++++++++ 13 files changed, 224 insertions(+), 132 deletions(-) create mode 100644 arch/arm/mach-tegra/pllx.h create mode 100644 arch/arm/mach-tegra/tegra114/pllx.c create mode 100644 arch/arm/mach-tegra/tegra124/pllx.c create mode 100644 arch/arm/mach-tegra/tegra20/pllx.c create mode 100644 arch/arm/mach-tegra/tegra210/pllx.c create mode 100644 arch/arm/mach-tegra/tegra30/pllx.c
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index f7285eb0de8c..e3c27845174a 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -11,122 +11,10 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include "cpu.h" +#include "pllx.h" #include "pmc.h" #include "scu.h"
-/* - * Timing tables for each SOC for all four oscillator options. - */ -struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { - /* - * T20: 1 GHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 22:20 3 - * PLLX_BASE n 17: 8 10 - * PLLX_BASE m 4: 0 5 - * PLLX_MISC cpcon 11: 8 4 - */ - { - { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ - { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ - { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ - { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - /* - * T25: 1.2 GHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 22:20 3 - * PLLX_BASE n 17: 8 10 - * PLLX_BASE m 4: 0 5 - * PLLX_MISC cpcon 11: 8 4 - */ - { - { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ - { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ - { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ - { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - /* - * T30: 600 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 22:20 3 - * PLLX_BASE n 17: 8 10 - * PLLX_BASE m 4: 0 5 - * PLLX_MISC cpcon 11: 8 4 - */ - { - { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ - { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ - { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ - { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - /* - * T114: 700 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 23:20 4 - * PLLX_BASE n 15: 8 8 - * PLLX_BASE m 7: 0 8 - */ - { - { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ - { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ - { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ - { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - - /* - * T124: 700 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 23:20 4 - * PLLX_BASE n 15: 8 8 - * PLLX_BASE m 7: 0 8 - */ - { - { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ - { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ - { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ - { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ - { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ - }, - - /* - * T210: 700 MHz - * - * Register Field Bits Width - * ------------------------------ - * PLLX_BASE p 24:20 5 - * PLLX_BASE n 15: 8 8 - * PLLX_BASE m 7: 0 8 - */ - { - { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/ - { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ - { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ - { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ - { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ - { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ - }, -}; - static inline void pllx_set_iddq(void) { #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) @@ -206,22 +94,16 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int chip_sku; enum clock_osc_freq osc; - struct clk_pll_table *sel; + const struct clk_pll_table *sel; debug("%s entry\n", __func__);
- /* get SKU info */ - /* get chip SKU, combo of the above info */ - chip_sku = tegra_get_chip_sku(); - debug("%s: Chip SKU = %d\n", __func__, chip_sku); - /* get osc freq */ osc = clock_get_osc_freq(); debug("%s: osc = %d\n", __func__, osc);
/* set pllx */ - sel = &tegra_pll_x_table[chip_sku][osc]; + sel = tegra_get_pllx_table(); pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); }
diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 9e5bf39ebfd7..e17ccefb663b 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -49,13 +49,6 @@
#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-struct clk_pll_table { - u16 n; - u16 m; - u8 p; - u8 cpcon; -}; - void clock_enable_coresight(int enable); void enable_cpu_clock(int enable); void halt_avp(void) __attribute__ ((noreturn)); diff --git a/arch/arm/mach-tegra/pllx.h b/arch/arm/mach-tegra/pllx.h new file mode 100644 index 000000000000..5a68b65b89d5 --- /dev/null +++ b/arch/arm/mach-tegra/pllx.h @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA_PLLX_H +#define _TEGRA_PLLX_H + +struct clk_pll_table { + u16 n; + u16 m; + u8 p; + u8 cpcon; +}; + +const struct clk_pll_table *tegra_get_pllx_table(void); + +#endif diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index ea7f7b717a51..fd56b6a02f6e 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. # # SPDX-License-Identifier: GPL-2.0 # @@ -7,3 +7,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o funcmux.o pinmux.o +obj-y += pllx.o diff --git a/arch/arm/mach-tegra/tegra114/pllx.c b/arch/arm/mach-tegra/tegra114/pllx.c new file mode 100644 index 000000000000..4c4e8f74f973 --- /dev/null +++ b/arch/arm/mach-tegra/tegra114/pllx.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra114_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T114: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra114_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index c00de6151e2d..e9554ccc966a 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2013-2014 +# (C) Copyright 2013-2016 # NVIDIA Corporation <www.nvidia.com> # # SPDX-License-Identifier: GPL-2.0+ @@ -10,6 +10,7 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o +obj-y += pllx.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o
diff --git a/arch/arm/mach-tegra/tegra124/pllx.c b/arch/arm/mach-tegra/tegra124/pllx.c new file mode 100644 index 000000000000..c19f1df6014b --- /dev/null +++ b/arch/arm/mach-tegra/tegra124/pllx.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra124_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T124: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra124_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 3cf1e7f113ce..0c2b5d51c73f 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -13,6 +13,7 @@ endif CFLAGS_warmboot_avp.o += -march=armv4t
obj-y += clock.o funcmux.o pinmux.o +obj-y += pllx.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o obj-$(CONFIG_TEGRA20_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/mach-tegra/tegra20/pllx.c b/arch/arm/mach-tegra/tegra20/pllx.c new file mode 100644 index 000000000000..f094f06d7fed --- /dev/null +++ b/arch/arm/mach-tegra/tegra20/pllx.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra20_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T20: 1 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +static const struct clk_pll_table tegra25_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T25: 1.2 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + int chip_sku; + + chip_sku = tegra_get_chip_sku(); + if (chip_sku == TEGRA_SOC_T25) + return tegra25_pll_x_table; + else + return tegra20_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index b6012fc7baac..dfc0a9b8e702 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2013-2015 +# (C) Copyright 2013-2016 # NVIDIA Corporation <www.nvidia.com> # # SPDX-License-Identifier: GPL-2.0+ @@ -8,5 +8,6 @@ obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o +obj-y += pllx.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra210/pllx.c b/arch/arm/mach-tegra/tegra210/pllx.c new file mode 100644 index 000000000000..9c6f0e0013da --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/pllx.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra210_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T210: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 24:20 5 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ + { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ + { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra210_pll_x_table; +} diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index d3d3b6e7c4fd..fd56b6a02f6e 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -1,5 +1,5 @@ # -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. +# Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. # # SPDX-License-Identifier: GPL-2.0 # @@ -7,3 +7,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o
obj-y += clock.o funcmux.o pinmux.o +obj-y += pllx.o diff --git a/arch/arm/mach-tegra/tegra30/pllx.c b/arch/arm/mach-tegra/tegra30/pllx.c new file mode 100644 index 000000000000..7c4f0ab67f1c --- /dev/null +++ b/arch/arm/mach-tegra/tegra30/pllx.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/arch-tegra/clock.h> +#include "../cpu.h" +#include "../pllx.h" + +static const struct clk_pll_table tegra30_pll_x_table[CLOCK_OSC_FREQ_COUNT] = { + /* + * T30: 600 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ +}; + +const struct clk_pll_table *tegra_get_pllx_table(void) +{ + return tegra30_pll_x_table; +}