On 03/15/2015 12:20 PM, Marek Vasut wrote:
On Sunday, March 15, 2015 at 05:04:05 PM, Stephen Warren wrote:
On 03/13/2015 12:13 AM, Stephen Warren wrote:
BCM2835 bus addresses use the top 2 bits to determine whether peripherals use or bypass the GPU L1 and L2 cache. BCM2835-ARM-Peripherals.pdf states that: ...
If you do end up applying this, the subject should say phys->bus not phys->virt.
I'd say we should wait a bit until these patches stabilize a little more, don't you think so ?
I can see the argument. That said, I don't expect anything much to "stabilize" about the patches; they appear to work!
It would be nice though if someone from the RPi Foundation could comment on the exact effect of the upper bus address bits, and why 0xc would work for RPi2 but 0x4 for the RPi 1. I wonder if the ARM cache status (enabled, disabled) interacts with the GPU cache enable in any way, e.g. burst vs. non-burst transactions on the bus or something? That's about the only reason I can see for the RPi Foundation kernel working with 0x4 bus addresses on both chips, but U-Boot needing something different on RPi2...
Dom, for reference, see: http://lists.denx.de/pipermail/u-boot/2015-March/207947.html http://lists.denx.de/pipermail/u-boot/2015-March/thread.html#207947