Some variants of the Gumstix Pepper board use DDR3 memory instead of DDR2. This adds a machine variant to support these DDR3-based boards which can be built as 'pepper_ddr3_defconfig' rather than the normal 'pepper_defconfig'.
Signed-off-by: Ash Charles ashcharles@gmail.com --- board/gumstix/pepper/MAINTAINERS | 1 + board/gumstix/pepper/board.c | 95 ++++++++++++++++++++++++++++++---------- configs/pepper_ddr3_defconfig | 4 ++ 3 files changed, 77 insertions(+), 23 deletions(-) create mode 100644 configs/pepper_ddr3_defconfig
diff --git a/board/gumstix/pepper/MAINTAINERS b/board/gumstix/pepper/MAINTAINERS index ae860ec..7132095 100644 --- a/board/gumstix/pepper/MAINTAINERS +++ b/board/gumstix/pepper/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/gumstix/pepper/ F: include/configs/pepper.h F: configs/pepper_defconfig +F: configs/pepper_ddr3_defconfig diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index f644f81..fbbca3b 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -33,13 +33,55 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD -static const struct ddr_data ddr2_data = { +#define OSC (V_OSCK/1000000) + +#ifdef CONFIG_USE_DDR3 +static const struct ddr_data ddr_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +const struct dpll_params dpll_ddr = {400, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +#else +static const struct ddr_data ddr_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, };
-static const struct cmd_control ddr2_cmd_ctrl_data = { +static const struct cmd_control ddr_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd1csratio = MT47H128M16RT25E_RATIO, @@ -47,7 +89,7 @@ static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd2csratio = MT47H128M16RT25E_RATIO, };
-static const struct emif_regs ddr2_emif_reg_data = { +static const struct emif_regs ddr_emif_reg_data = { .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, @@ -56,6 +98,33 @@ static const struct emif_regs ddr2_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, };
+const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; +#endif /* CONFIG_USE_DDR3 */ + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void sdram_init(void) +{ +#ifdef CONFIG_USE_DDR3 + config_ddr(400, &ioregs_ddr, &ddr_data, + &ddr_cmd_ctrl_data, &ddr_emif_reg_data, 0); +#else + config_ddr(266, &ioregs_ddr, &ddr_data, + &ddr_cmd_ctrl_data, &ddr_emif_reg_data, 0); +#endif +} + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -64,14 +133,6 @@ int spl_start_uboot(void) } #endif
-#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -82,19 +143,7 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); }
-const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, -};
-void sdram_init(void) -{ - config_ddr(266, &ioregs, &ddr2_data, - &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -} #endif
int board_init(void) diff --git a/configs/pepper_ddr3_defconfig b/configs/pepper_ddr3_defconfig new file mode 100644 index 0000000..8077399 --- /dev/null +++ b/configs/pepper_ddr3_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="USE_DDR3" +CONFIG_ARM=y +CONFIG_TARGET_PEPPER=y