From: Markus Niebel Markus.Niebel@tq-group.com
according to
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14802.htm...
and the clarification given by Marc Rutland of ARM
data cache invalidation should go from outer to inner cache. This patch corrects the order in
flush_dcache_range flush_dcache_all
Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- Changes for v2: - delete non related stuff (thanks to Hannes Schmelzer)
arch/arm/cpu/armv7/cache_v7.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a5aa4fa..81eb286 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -235,9 +235,9 @@ static void v7_inval_tlb(void)
void invalidate_dcache_all(void) { - v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); - v7_outer_cache_inval_all(); + + v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); }
/* @@ -257,9 +257,9 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); - v7_outer_cache_inval_range(start, stop); + + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); }
/*