[U-Boot] TLB mapping for pcie mem space for fsl corenet processors

hi, The tlb entries for the pcie mem space for the corenet SoC's is done for 1.5GiB but certain boards use all the 4 pcie controller instantiations, and each controller is assigned 512MiB size in the config files. Should the tlb entries not map 2GiB space as against 1.5GiB. Am i missing something. Thanks.

-sughosh