For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel.
Signed-off-by: Ye.Li B37916@freescale.com --- Changes since v2: - None
Changes since v1: - None
arch/arm/cpu/armv7/mx6/soc.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 6dc2600..c0bb431 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -239,6 +239,18 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); }
+#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + int arch_cpu_init(void) { init_aips(); @@ -254,6 +266,11 @@ int arch_cpu_init(void) if (mxc_get_clock(MXC_ARM_CLK) == 396000000) set_ahb_rate(132000000);
+ /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA