Hi Philippe,
On Mon, Mar 9, 2020 at 8:26 PM Philippe Schenker philippe.schenker@toradex.com wrote:
This patch determines which phy is placed on the board with the PHY ID then it sets the same settings for KSZ9031 as before but for KSZ9131 it enables both RXC and TXC delay lines in the PHY. This will compensate the missing delay from the MAC. Other skew settings are not needed as the traces on board are routed exactly the same length
Signed-off-by: Philippe Schenker philippe.schenker@toradex.com
board/toradex/verdin-imx8mm/verdin-imx8mm.c | 79 +++++++++++++++------ 1 file changed, 56 insertions(+), 23 deletions(-)
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 3177ba53907..57c4befcfdd 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -33,29 +33,62 @@ static int setup_fec(void)
int board_phy_config(struct phy_device *phydev) {
/** The PHY adds 1.2ns for the RXC and 0ns for TXC clock by* default. The MAC and the layout don't add a skew between* clock and data.* Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for* the TXC path to get the required clock skews.*//* control data pad skew - devaddr = 0x02, register = 0x04 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070);/* rx data pad skew - devaddr = 0x02, register = 0x05 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777);/* tx data pad skew - devaddr = 0x02, register = 0x06 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4);
int tmp;switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {case PHY_ID_KSZ9031:/** The PHY adds 1.2ns for the RXC and 0ns for TXC clock by* default. The MAC and the layout don't add a skew between* clock and data.* Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for* the TXC path to get the required clock skews.*//* control data pad skew - devaddr = 0x02, register = 0x04 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC,0x0070);/* rx data pad skew - devaddr = 0x02, register = 0x05 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC,0x7777);/* tx data pad skew - devaddr = 0x02, register = 0x06 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC,0x0000);/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,MII_KSZ9031_MOD_DATA_NO_POST_INC,0x03f4);break;case PHY_ID_KSZ9131:default:/* read rxc dll control - devaddr = 0x2, register = 0x4c */tmp = ksz9031_phy_extended_read(phydev, 0x02,MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,MII_KSZ9031_MOD_DATA_NO_POST_INC);/* disable rxdll bypass (enable 2ns skew delay on RXC) */tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */tmp = ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);/* read txc dll control - devaddr = 0x02, register = 0x4d */tmp = ksz9031_phy_extended_read(phydev, 0x02,MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,MII_KSZ9031_MOD_DATA_NO_POST_INC);/* disable txdll bypass (enable 2ns skew delay on TXC) */tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */tmp = ksz9031_phy_extended_write(phydev, 0x02,MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);break;} if (phydev->drv->config) phydev->drv->config(phydev);-- 2.25.1
Tested-by: Igor Opaniuk igor.opaniuk@toradex.com Acked-by: Igor Opaniuk igor.opaniuk@toradex.com