On Sat, 29 Jan 2022 16:58:43 +0100 Jernej Skrabec jernej.skrabec@gmail.com wrote:
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that it has to be set before read calibration and cleared afterwards. This is already done for first rank, but not for second (copy & paste error.)
Indeed looks like it, from the logic point of view.
Fix it.
Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support") Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com
Reviewed-by: Andre Przywara andre.przywara@arm.com
Applied to sunxi/master.
Cheers, Andre
arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 76f520f4e780..83e8abc2f8d8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para) } }
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);}
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);