Hi Tom,
Please pull the SoCFPGA changes as shown in below.
Thanks.
Best regards, Tien Fong
The following changes since commit c18e5fb055ab789f58434e3cb432582adee0134c:
dtoc: Update test_src_scan.py for new tegra compatibles (2022-06-14 13:59:23 -0400)
are available in the Git repository at:
https://github.com/tienfong/uboot_mainline.git 32e0379143b433e29d76404f5f4c279067e48853
for you to fetch changes up to 32e0379143b433e29d76404f5f4c279067e48853:
ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched (2022-06-17 16:27:05 +0800)
---------------------------------------------------------------- Dinesh Maniyam (5): arch: arm: socfpga: timer_s10: Override udelay for secure section arm: dts: socfpga: agilex: Add freeze controller node arm: dts: socfpga: stratix10: Add freeze controller node drivers: cache: ncore: Disable snoop filter ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched
Marek Vasut (1): arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script
Tien Fong Chee (3): intel: n5x: ddr: update license ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS ddr: altera: Stratix10: Use phys_size_t for memory size
Yau Wai Gan (1): arm: dts: socfpga: stratix10: Update MMC smplsel value
arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 ++++++++++- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++++++++++- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +- arch/arm/mach-socfpga/timer_s10.c | 34 +++++++++++++++++++++++++++++++++- drivers/cache/cache-ncore.c | 6 +++--- drivers/ddr/altera/sdram_n5x.c | 4 ++-- drivers/ddr/altera/sdram_s10.c | 4 ++-- drivers/ddr/altera/sdram_soc64.c | 5 +++-- drivers/ddr/altera/sdram_soc64.h | 2 +- include/configs/socfpga_vining_fpga.h | 3 ++- 10 files changed, 67 insertions(+), 15 deletions(-)