Re: [U-Boot] [PATCH 10/13] x86: braswell: Add microcode for B0/C0/D0 stepping SoC

On 15 August 2017 at 23:41, Bin Meng bmeng.cn@gmail.com wrote:

This adds microcode device tree fragment for Braswell B0 (406C2), C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

arch/x86/dts/microcode/m01406c2220.dtsi | 4308 +++++++++++++++++++++++++++++++ arch/x86/dts/microcode/m01406c3363.dtsi | 4308 +++++++++++++++++++++++++++++++ arch/x86/dts/microcode/m01406c440a.dtsi | 4308 +++++++++++++++++++++++++++++++ 3 files changed, 12924 insertions(+) create mode 100644 arch/x86/dts/microcode/m01406c2220.dtsi create mode 100644 arch/x86/dts/microcode/m01406c3363.dtsi create mode 100644 arch/x86/dts/microcode/m01406c440a.dtsi

Reviewed-by: Simon Glass sjg@chromium.org