Hi,
I will compare the code against the manual later, just one thing that popped up:
On 25/06/18 11:37, Icenowy Zheng wrote:
The new Allwinner H6 SoC has a brand new CCU layout.
Add clock code for it.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
arch/arm/include/asm/arch-sunxi/clock.h | 2 + .../include/asm/arch-sunxi/clock_sun50i_h6.h | 320 ++++++++++++++++++ arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/clock_sun50i_h6.c | 94 +++++ 4 files changed, 417 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h create mode 100644 arch/arm/mach-sunxi/clock_sun50i_h6.c
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h new file mode 100644 index 0000000000..e36937059b --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -0,0 +1,320 @@
...
+unsigned int clock_get_pll6(void) +{
- struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;- uint32_t rval = readl(&ccm->pll6_cfg);
- int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
- int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
CCM_PLL6_CTRL_DIV1_SHIFT) + 1;- int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;- /* The register defines PLL6-4X, not plain PLL6 */
- return 24000000 * n / div1 / div2 / 4;
I understand that this is copied from the other SoC's clock drivers, but the return line looks prone to overflows: If n > 178, then the result will be wrong. We probably won't go that high, but this can be easily fixed by moving the "/ 4" upfront, right after the 24000000.
Cheers, Andre.