Subject: Re: [PATCH 1/2] net: fec_mxc: Fix clk_ref rate on iMX93
Hi,
On 23. 09. 24 15:14, Peng Fan (OSS) wrote:
From: Ye Li ye.li@nxp.com
Because iMX93 has a internal 1/2 divider before clock input to
network
controller, so have to set twice frequency rate
Fixes: 09de565f76b ("net: fec_mxc: support i.MX93") Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com
drivers/net/fec_mxc.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0a0d92bc2cd..e5d7f0f3e1e 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1215,6 +1215,9 @@ static int fecmxc_set_ref_clk(struct clk
*clk_ref, phy_interface_t interface)
else return -EINVAL;
- if (is_imx93())
freq = freq << 1;Humm, but how did it work so far?
On phyboard-segin-imx93, this change breaks fec ethernet.
I had to revert this already in NXP downstream u-boot.
Ah. If you set enet_ref_clk to 250M, then you no need this change. Otherwise you need this change.
Regards, Peng.
BR, Primoz
- ret = clk_set_rate(clk_ref, freq); if (ret < 0) return ret;
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