The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property.
Signed-off-by: Timur Tabi timur@freescale.com --- arch/powerpc/cpu/mpc85xx/fdt.c | 13 +++++++------ 1 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 642f6c5..7a2600a 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -165,7 +165,6 @@ static inline void ft_fixup_l2cache(void *blob) int len, off; u32 *ph; struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); - char compat_buf[38];
const u32 line_size = 32; const u32 num_ways = 8; @@ -192,22 +191,24 @@ static inline void ft_fixup_l2cache(void *blob) }
if (cpu) { + char compat_buf[40]; + if (isdigit(cpu->name[0])) len = sprintf(compat_buf, - "fsl,mpc%s-l2-cache-controller", cpu->name); + "fsl,mpc%s-l2-cache-controller%ccache", + cpu->name, 0); else len = sprintf(compat_buf, - "fsl,%c%s-l2-cache-controller", - tolower(cpu->name[0]), cpu->name + 1); + "fsl,%c%s-l2-cache-controller%ccache", + tolower(cpu->name[0]), cpu->name + 1, 0);
- sprintf(&compat_buf[len + 1], "cache"); + fdt_setprop(blob, off, "compatible", compat_buf, len + 1); } fdt_setprop(blob, off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, off, "cache-block-size", line_size); fdt_setprop_cell(blob, off, "cache-size", size); fdt_setprop_cell(blob, off, "cache-sets", num_sets); fdt_setprop_cell(blob, off, "cache-level", 2); - fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
/* we dont bother w/L3 since no platform of this type has one */ }