hi,
Am 03.04.2013 11:00, schrieb Albert ARIBAUD:
apt-get install uboot-envtools fw_printenv bootcmd
No result there? There should be.
sure. it's what I set into bootcmd.bak:
fw_setenv bootcmd.bak 'nand read.e 0x1200000 0x200000 0x600000;nand read.e 0x2000000 0x800000 0x1000000;bootm 0x1200000 0x2000000'
the outputs all looked fine, after I changed the offset in config file to 0x0. Else I wouln't have written anything. But still I am not 100% sure about the sector size of 0x20000 (128KByte)
Yes: get control through JTAG.
Ok. I'll try.
Don't consider unsoldering / resoldering, all the more if sockets are involved, as long as you board has JTAG, either as a header or at least as contact points. A dumb JTAG probe and OpenOCD will cost you little and go a long way.
I've got the following soldering points:
- a 1x3 Pin@2,54mm connector labeld J7 which could be a FAN connector.
- a 2x5=10 PIN@2mm connector J1 near the ROM chip.
both connectors are on this picture: http://natisbad.org/NAS/pics/NETGEAR_ReadyNAS_Duo_v2_RND2000-200EUS_J1_and_J...
- 1x4 PIN @ 2,54mm connector.
So which one? Do I have to guess the pins?
which probe should I chose? Something like these? - Embedded Projects OpenOCD-USB Adapter - Xilinx JTAG Parallel Cable III FPGA CPLD programmer LPT - SainSmart USB Blaster Programmer Cable For FPGA CPLD JTAG Development Board - found a LPT programmer having nothing more than a 74HC244 chip.
Id' prefer the USB adapter...
btw, I found out there is a boot menu. When I hold the reset button during bootup, there is a boot menu offering:
Normal.
Factory default. I believe it loads the initrd to reformat the harddrives.
OS Re-install. Installs the root fs to hard drive from JFFS rom.
Skip volume check.
Memory test. Performs a memory test.
Disk test. Maybe Smart test.
I tried most. They all freeze after printing "net: egiga..." except memory test. Won't help much, I believe, since most rely on the boot process which is broken.
JPT