On Jan 28, 2011, at 8:17 AM, Fabian Cenedese wrote:
Hi
Since I updated to the last u-boot version my board keeps stalling in a newly added loop in ddr3-gen.c. At the end of the function fsl_ddr_set_memctl_regs is a loop that tests an undocumented register (at least it's not in the reference manuals).
while (!(in_be32(&ddr->debug[1]) & 0x2)) ;
This register seems to be always 0 (from debugging with a jtag debugger). Therefore it waits here forever. If I move the cpu beyond this loop or take the loop out completely then u-boot starts up happily, including init of ddr and relocating.
Is this loop necessary for my cpu? Should that be made configurable? Here are the technical details from u-boot itself:
CPU0: P2020E, Version: 2.0, (0x80ea0020) Core: E500, Version: 5.0, (0x80211050) Clock Configuration: CPU0:1200 MHz, CPU1:1200 MHz, CCB:600 MHz, DDR:400 MHz (800 MT/s data rate) (Asynchronous), LBC:37.500 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: gin-pcie I2C: ready DRAM: Detected UDIMM(s) DDR: 1 GiB (DDR3, 64-bit, CL=6, ECC off) Testing 0x00000000 - 0x3fffffff Remap DDR POST memory PASSED L2: 512 KB enabled Using default environment
Thanks
bye Fabi
See this patch seq:
http://lists.denx.de/pipermail/u-boot/2011-January/086200.html
- k