diff -urN -x CVS u-boot/Makefile u-boot-i386/Makefile
--- u-boot/Makefile	Mon Apr 28 00:52:51 2003
+++ u-boot-i386/Makefile	Mon Apr 28 12:39:12 2003
@@ -60,7 +60,11 @@
 CROSS_COMPILE = arm-linux-
 endif
 ifeq ($(ARCH),i386)
-#CROSS_COMPILE = i386-elf-
+ifeq ($(HOSTARCH),i386)
+CROSS_COMPILE =
+else
+CROSS_COMPILE = i386-linux-
+endif
 endif
 ifeq ($(ARCH),mips)
 CROSS_COMPILE = mips_4KC-
@@ -706,6 +710,12 @@
 sc520_cdp_config	:	unconfig
 	@./mkconfig $(@:_config=) i386 i386 sc520_cdp
 
+sc520_spunk_config	:	unconfig
+	@./mkconfig $(@:_config=) i386 i386 sc520_spunk
+
+sc520_spunk_rel_config	:	unconfig
+	@./mkconfig $(@:_config=) i386 i386 sc520_spunk
+
 #========================================================================
 # MIPS
 #========================================================================
@@ -729,7 +739,8 @@
 		| xargs rm -f
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
-	      examples/mem_to_mem_idma2intr
+	      examples/mem_to_mem_idma2intr examples/82559_eeprom
+
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
 	rm -f tools/easylogo/easylogo tools/bmp_logo
 	rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
diff -urN -x CVS u-boot/board/sc520_cdp/config.mk u-boot-i386/board/sc520_cdp/config.mk
--- u-boot/board/sc520_cdp/config.mk	Mon Nov 18 01:14:45 2002
+++ u-boot-i386/board/sc520_cdp/config.mk	Wed Nov 20 14:15:45 2002
@@ -22,4 +22,4 @@
 #
 
 
-TEXT_BASE = 0x387e0000
+TEXT_BASE = 0x387c0000
diff -urN -x CVS u-boot/board/sc520_cdp/flash.c u-boot-i386/board/sc520_cdp/flash.c
--- u-boot/board/sc520_cdp/flash.c	Fri Nov 22 00:11:51 2002
+++ u-boot-i386/board/sc520_cdp/flash.c	Wed Apr  2 08:50:16 2003
@@ -1,5 +1,8 @@
 /*
  * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, daniel@omicron.se
+ * 
+ * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Alex Zuepke <azu@sysgo.de>
  *
@@ -23,15 +26,21 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 
 ulong myflush(void);
 
 
-#define FLASH_BANK_SIZE 0x400000	/* 4 MB */
-#define MAIN_SECT_SIZE  0x20000		/* 128 KB */
+#define SC520_MAX_FLASH_BANKS  3
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANK1_BASE 0x30000000  /* ROMCS0 */
+#define SC520_FLASH_BANK2_BASE 0x28000000  /* ROMCS1 */
+#define SC520_FLASH_BANKSIZE   0x8000000
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+#define AMD29LV016_SIZE        0x200000
+#define AMD29LV016_SECTORS     32
 
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
 
 #define CMD_READ_ARRAY		0x00F000F0
 #define CMD_UNLOCK1		0x00AA00AA
@@ -41,8 +50,6 @@
 #define CMD_PROGRAM		0x00A000A0
 #define CMD_UNLOCK_BYPASS	0x00200020
 
-#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
-#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
 
 #define BIT_ERASE_DONE		0x00800080
 #define BIT_RDY_MASK		0x00800080
@@ -58,392 +65,392 @@
 
 ulong flash_init(void)
 {
-    int i, j;
-    ulong size = 0;
-
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
-    {
-	ulong flashbase = 0;
-	flash_info[i].flash_id =
-	  (AMD_MANUFACT & FLASH_VENDMASK) |
-	  (AMD_ID_LV160B & FLASH_TYPEMASK);
-	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
-	if (i == 0)
-	  flashbase = PHYS_FLASH_1;
-	else
-	  panic("configured to many flash banks!\n");
-	for (j = 0; j < flash_info[i].sector_count; j++)
-	{
-
-	    if (j <= 3)
-	    {
-		/* 1st one is 32 KB */
-		if (j == 0)
-		{
-			flash_info[i].start[j] = flashbase + 0;
-		}
-
-		/* 2nd and 3rd are both 16 KB */
-		if ((j == 1) || (j == 2))
-		{
-			flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000;
-		}
-
-		/* 4th 64 KB */
-		if (j == 3)
-		{
-			flash_info[i].start[j] = flashbase + 0x10000;
-		}
-	    }
-	    else
-	    {
-		flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE;
-	    }
-	}
-	size += flash_info[i].size;
-    }
-
-    /*
-     * Protect monitor and environment sectors
-     */
-    flash_protect(FLAG_PROTECT_SET,
-		  i386boot_start-CFG_FLASH_BASE,
-		  i386boot_end-CFG_FLASH_BASE,
-		  &flash_info[0]);
-
-    flash_protect(FLAG_PROTECT_SET,
-		  CFG_ENV_ADDR,
-		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-		  &flash_info[0]);
-    return size;
+	int i, j;
+	ulong size = 0;
+	
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		int sectsize = 0; 
+		if (i==0 || i==2) {
+			/* FixMe: this assumes that bank 0 and 2 
+			 * are mapped to the two 8Mb banks */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV016B & FLASH_TYPEMASK);
+			
+			flash_info[i].size = AMD29LV016_SIZE*4;
+			flash_info[i].sector_count = AMD29LV016_SECTORS;
+			sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS;
+		} else {
+			/* FixMe: this assumes that bank1 is unmapped 
+			 * (or mapped to the same flash bank as BOOTCS) */
+			flash_info[i].flash_id = 0;
+			flash_info[i].size = 0;
+			flash_info[i].sector_count = 0;
+			sectsize=0;
+		}
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		case 1:
+			flashbase = SC520_FLASH_BANK1_BASE;
+			break;
+		case 2:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		default:
+			panic("configured to many flash banks!\n");
+		}
+		
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = sectsize;
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+	}
+	
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start-SC520_FLASH_BANK0_BASE,
+		      i386boot_end-SC520_FLASH_BANK0_BASE,
+		      &flash_info[0]);
+	
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+	return size;
 }
 
 /*-----------------------------------------------------------------------
  */
-void flash_print_info  (flash_info_t *info)
+void flash_print_info(flash_info_t *info)
 {
-    int i;
-
-    switch (info->flash_id & FLASH_VENDMASK)
-    {
-    case (AMD_MANUFACT & FLASH_VENDMASK):
-	printf("AMD: ");
-	break;
-    default:
-	printf("Unknown Vendor ");
-	break;
-    }
-
-    switch (info->flash_id & FLASH_TYPEMASK)
-    {
-    case (AMD_ID_LV160B & FLASH_TYPEMASK):
-	printf("2x Amd29F160BB (16Mbit)\n");
-	break;
-    default:
-	printf("Unknown Chip Type\n");
-	goto Done;
-	break;
-    }
-
-    printf("  Size: %ld MB in %d Sectors\n",
-	   info->size >> 20, info->sector_count);
-
-    printf("  Sector Start Addresses:");
-    for (i = 0; i < info->sector_count; i++)
-    {
-	if ((i % 5) == 0)
-	{
-	    printf ("\n   ");
-	}
-	printf (" %08lX%s", info->start[i],
-		info->protect[i] ? " (RO)" : "     ");
-    }
-    printf ("\n");
+	int i;
 
-Done:
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD: ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV016B & FLASH_TYPEMASK):
+		printf("4x Amd29LV016B (16Mbit)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		goto done;
+		break;
+	}
+	
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	
+	done:
 }
 
 /*-----------------------------------------------------------------------
  */
 
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
 {
-    ulong result;
-    int iflag, prot, sect;
-    int rc = ERR_OK;
-    int chip1, chip2;
-
-    /* first look for protection bits */
-
-    if (info->flash_id == FLASH_UNKNOWN)
-	return ERR_UNKNOWN_FLASH_TYPE;
-
-    if ((s_first < 0) || (s_first > s_last)) {
-	return ERR_INVAL;
-    }
-
-    if ((info->flash_id & FLASH_VENDMASK) !=
-	(AMD_MANUFACT & FLASH_VENDMASK)) {
-	return ERR_UNKNOWN_FLASH_VENDOR;
-    }
-
-    prot = 0;
-    for (sect=s_first; sect<=s_last; ++sect) {
-	if (info->protect[sect]) {
-	    prot++;
-	}
-    }
-    if (prot)
-	return ERR_PROTECTED;
-
-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
-    iflag = disable_interrupts();
-
-    /* Start erase on unprotected sectors */
-    for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
-    {
-	printf("Erasing sector %2d ... ", sect);
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer();
-
-	if (info->protect[sect] == 0)
-	{	/* not protected */
-	    vu_long *addr = (vu_long *)(info->start[sect]);
-
-	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	    MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
-	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	    *addr = CMD_ERASE_CONFIRM;
-
-	    /* wait until flash is ready */
-	    chip1 = chip2 = 0;
-
-	    do
-	    {
-		result = *addr;
-
-		/* check timeout */
-		if (get_timer(0) > CFG_FLASH_ERASE_TOUT)
-		{
-		    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-		    chip1 = TMO;
-		    break;
+	ulong result;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1, chip2;
+
+	/* first look for protection bits */
+	
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+	
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+	
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
 		}
-
-		if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
-			chip1 = READY;
-
-		if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
-			chip1 = ERR;
-
-		if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
-			chip2 = READY;
-
-		if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
-			chip2 = ERR;
-
-	    }  while (!chip1 || !chip2);
-
-	    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
-	    if (chip1 == ERR || chip2 == ERR)
-	    {
-		rc = ERR_PROG_ERROR;
-		goto outahere;
-	    }
-	    if (chip1 == TMO)
-	    {
-		rc = ERR_TIMOUT;
-		goto outahere;
-	    }
-
-	    printf("ok.\n");
-	}
-	else /* it was protected */
-	{
-	    printf("protected!\n");
 	}
-    }
-
-    if (ctrlc())
-      printf("User Interrupt!\n");
+	if (prot) {
+		return ERR_PROTECTED;
+	}
+	
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts();
+	
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+		printf("Erasing sector %2d ... ", sect);
+		
+		/* arm simple, non interrupt dependent timer */
+		reset_timer();
+		
+		if (info->protect[sect] == 0) {	
+			/* not protected */
+			ulong addr = info->start[sect];
+			
+			writel(CMD_UNLOCK1, addr + 1);
+			writel(CMD_UNLOCK2, addr + 2);
+			writel(CMD_ERASE_SETUP, addr + 1);
+			
+			writel(CMD_UNLOCK1, addr + 1);
+			writel(CMD_UNLOCK2, addr + 2);
+			writel(CMD_ERASE_CONFIRM, addr);
+
+			
+			/* wait until flash is ready */
+			chip1 = chip2 = 0;
+			
+			do {
+				result = readl(addr);
+				
+				/* check timeout */
+				if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+					writel(CMD_READ_ARRAY, addr + 1);
+					chip1 = TMO;
+					break;
+				}
+				
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) {
+					chip1 = READY;
+				}
+				
+				if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) {
+					chip1 = ERR;
+				}
+				
+				if (!chip2 && (result >> 16) & BIT_ERASE_DONE) {
+					chip2 = READY;
+				}
+				
+				if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) {
+					chip2 = ERR;
+				}
+				
+			}  while (!chip1 || !chip2);
+			
+			writel(CMD_READ_ARRAY, addr + 1);
+			
+			if (chip1 == ERR || chip2 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+			
+			printf("ok.\n");
+		} else { /* it was protected */
+			
+			printf("protected!\n");
+		}
+	}
+	
+	if (ctrlc()) {
+		printf("User Interrupt!\n");
+	}
 
 outahere:
-    /* allow flash to settle - wait 10 ms */
-    udelay(10000);
-
-    if (iflag)
-      enable_interrupts();
-
-
-    return rc;
+	/* allow flash to settle - wait 10 ms */
+	udelay(10000);
+	
+	if (iflag) {
+		enable_interrupts();
+	}
+	
+	return rc;
 }
 
 /*-----------------------------------------------------------------------
  * Copy memory to flash
  */
 
-volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+volatile static int write_word(flash_info_t *info, ulong dest, ulong data)
 {
-    vu_long *addr = (vu_long *)dest;
-    ulong result;
-    int rc = ERR_OK;
-    int iflag;
-    int chip1, chip2;
-
-    /*
-     * Check if Flash is (sufficiently) erased
-     */
-    result = *addr;
-    if ((result & data) != data)
-        return ERR_NOT_ERASED;
-
-
-    /*
-     * Disable interrupts which might cause a timeout
-     * here. Remember that our exception vectors are
-     * at address 0 in the flash, and we don't want a
-     * (ticker) exception to happen while the flash
-     * chip is in programming mode.
-     */
-    iflag = disable_interrupts();
-
-    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-    MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
-    *addr = CMD_PROGRAM;
-    *addr = data;
-
-    /* arm simple, non interrupt dependent timer */
-    reset_timer();
-
-    /* wait until flash is ready */
-    chip1 = chip2 = 0;
-    do
-    {
-	result = *addr;
-
-	/* check timeout */
-	if (get_timer(0) > CFG_FLASH_ERASE_TOUT)
-	{
-	    chip1 = ERR | TMO;
-	    break;
-	}
-	if (!chip1 && ((result & 0x80) == (data & 0x80)))
-		chip1 = READY;
-
-	if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
-	{
-		result = *addr;
-
-		if ((result & 0x80) == (data & 0x80))
+	ulong addr = dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+	int chip1, chip2;
+	
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = readl(addr);
+	if ((result & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+	
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts();
+
+	writel(CMD_UNLOCK1, addr + 1);
+	writel(CMD_UNLOCK2, addr + 2);
+	writel(CMD_UNLOCK_BYPASS, addr + 1);
+	writel(addr, CMD_PROGRAM);
+	writel(addr, data);
+	
+	/* arm simple, non interrupt dependent timer */
+	reset_timer();
+	
+	/* wait until flash is ready */
+	chip1 = chip2 = 0;
+	do {
+		result = readl(addr);
+		
+		/* check timeout */
+		if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		
+		if (!chip1 && ((result & 0x80) == (data & 0x80))) {
 			chip1 = READY;
-		else
-			chip1 = ERR;
-	}
-
-	if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
-		chip2 = READY;
-
-	if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR))
-	{
-		result = *addr;
-
-		if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
+		}
+		
+		if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = readl(addr);
+			
+			if ((result & 0x80) == (data & 0x80)) {
+				chip1 = READY;
+			} else {
+				chip1 = ERR;
+			}
+		}
+		
+		if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) {
 			chip2 = READY;
-		else
-			chip2 = ERR;
+		}
+		
+		if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) {
+			result = readl(addr);
+			
+			if ((result & (0x80 << 16)) == (data & (0x80 << 16))) {
+				chip2 = READY;
+			} else {
+				chip2 = ERR;
+			}
+		}
+		
+	}  while (!chip1 || !chip2);
+	
+	writel(CMD_READ_ARRAY, addr);
+	
+	if (chip1 == ERR || chip2 == ERR || readl(addr) != data) {
+		rc = ERR_PROG_ERROR;
 	}
-
-    }  while (!chip1 || !chip2);
-
-    *addr = CMD_READ_ARRAY;
-
-    if (chip1 == ERR || chip2 == ERR || *addr != data)
-        rc = ERR_PROG_ERROR;
-
-    if (iflag)
-      enable_interrupts();
-
-
-    return rc;
+	
+	if (iflag) {
+		enable_interrupts();
+	}
+	
+	return rc;
 }
 
 /*-----------------------------------------------------------------------
  * Copy memory to flash.
  */
 
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
-    ulong cp, wp, data;
-    int l;
-    int i, rc;
-
-    wp = (addr & ~3);	/* get lower word aligned address */
-
-    /*
-     * handle unaligned start bytes
-     */
-    if ((l = addr - wp) != 0) {
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+	
+	wp = (addr & ~3);	/* get lower word aligned address */
+	
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+		
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+	
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long*)src);
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
+	}
+	
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+	
+	/*
+	 * handle unaligned tail bytes
+	 */
 	data = 0;
-	for (i=0, cp=wp; i<l; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 24);
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
 	}
-	for (; i<4 && cnt>0; ++i) {
-	    data = (data >> 8) | (*src++ << 24);
-	    --cnt;
-	    ++cp;
-	}
-	for (; cnt==0 && i<4; ++i, ++cp) {
-	    data = (data >> 8) | (*(uchar *)cp << 24);
-	}
-
-	if ((rc = write_word(info, wp, data)) != 0) {
-	    return (rc);
-	}
-	wp += 4;
-    }
-
-    /*
-     * handle word aligned part
-     */
-    while (cnt >= 4) {
-	data = *((vu_long*)src);
-	if ((rc = write_word(info, wp, data)) != 0) {
-	    return (rc);
-	}
-	src += 4;
-	wp  += 4;
-	cnt -= 4;
-    }
-
-    if (cnt == 0) {
-	return ERR_OK;
-    }
-
-    /*
-     * handle unaligned tail bytes
-     */
-    data = 0;
-    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-	data = (data >> 8) | (*src++ << 24);
-	--cnt;
-    }
-    for (; i<4; ++i, ++cp) {
-	data = (data >> 8) | (*(uchar *)cp << 24);
-    }
-
-    return write_word(info, wp, data);
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+	
+	return write_word(info, wp, data);
 }
diff -urN -x CVS u-boot/board/sc520_cdp/sc520_cdp.c u-boot-i386/board/sc520_cdp/sc520_cdp.c
--- u-boot/board/sc520_cdp/sc520_cdp.c	Fri Feb 28 01:49:47 2003
+++ u-boot-i386/board/sc520_cdp/sc520_cdp.c	Wed Apr 30 12:48:48 2003
@@ -1,4 +1,5 @@
 /*
+ * 
  * (C) Copyright 2002
  * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
  *
@@ -24,109 +25,161 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/io.h>
+#include <asm/pci.h>
 #include <asm/ic/sc520.h>
 #include <asm/ic/ali512x.h>
 
+#undef SC520_CDP_DEBUG
+
+#ifdef	SC520_CDP_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
 /* ------------------------------------------------------------------------- */
 
+	
+/* 
+ * Theory:
+ * We first set up all IRQs to be non-pci, edge triggered,
+ * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets 
+ * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
+ * as needed. Whe choose the irqs to gram from a configurable list
+ * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
+ * such as 0 thngas will not work)
+ */
+
 static void irq_init(void)
 {
-	
 	/* disable global interrupt mode */
 	write_mmcr_byte(SC520_PICICR, 0x40); 
 	
-	/* set irq0-7 to edge */
+	/* set all irqs to edge */
 	write_mmcr_byte(SC520_MPICMODE, 0x00);
-	
-	/* set irq9-12 to level, all the other (8, 13-15) are edge */
-	write_mmcr_byte(SC520_SL1PICMODE, 0x1e);
-	
-	/* set irq16-24 (unused slave pic2) to level */
-	write_mmcr_byte(SC520_SL2PICMODE, 0xff);
+	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
+	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
 	
 	/* active low polarity on PIC interrupt pins, 
-	   active high polarity on all other irq pins */
-	write_mmcr_word(SC520_INTPINPOL, 0);
+	 *  active high polarity on all other irq pins */
+	write_mmcr_word(SC520_INTPINPOL, 0x0000);
 
 	/* set irq number mapping */
-	write_mmcr_byte(SC520_GPTMR0MAP,0);            /* disable GP timer 0 INT */       
-	write_mmcr_byte(SC520_GPTMR1MAP,0);            /* disable GP timer 1 INT */
-	write_mmcr_byte(SC520_GPTMR2MAP,0);            /* disable GP timer 2 INT */
-	write_mmcr_byte(SC520_PIT0MAP,0x1);            /* Set PIT timer 0 INT to IRQ0 */ 
-	write_mmcr_byte(SC520_PIT1MAP,0);              /* diable PIT timer 1 INT */
-	write_mmcr_byte(SC520_PIT2MAP,0);              /* diable PIT timer 2 INT */
-	write_mmcr_byte(SC520_PCIINTAMAP,0x4);         /* Set PCI INT A to IRQ9 */
-	write_mmcr_byte(SC520_PCIINTBMAP,0x5);         /* Set PCI INT B to IRQ10 */
-	write_mmcr_byte(SC520_PCIINTCMAP,0x6);         /* Set PCI INT C to IRQ11 */
-	write_mmcr_byte(SC520_PCIINTDMAP,0x7);         /* Set PCI INT D to IRQ12 */
-	write_mmcr_byte(SC520_DMABCINTMAP,0);          /* disable DMA INT */ 
-	write_mmcr_byte(SC520_SSIMAP,0);               /* disable Synchronius serial INT */
-	write_mmcr_byte(SC520_WDTMAP,0);               /* disable Watchdor INT */
-	write_mmcr_byte(SC520_RTCMAP,0x3);             /* Set RTC int to 8 */
-	write_mmcr_byte(SC520_WPVMAP,0);               /* disable write protect INT */
-	write_mmcr_byte(SC520_ICEMAP,0x2);             /* Set ICE Debug Serielport INT to IRQ1 */
-	write_mmcr_byte(SC520_FERRMAP,0x8);            /* Set FP error INT to IRQ13 */
-	write_mmcr_byte(SC520_GP0IMAP,6);              /* Set GPIRQ0 (ISA IRQ2) to IRQ9 */
-	write_mmcr_byte(SC520_GP1IMAP,2);              /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
-	write_mmcr_byte(SC520_GP2IMAP,7);              /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */       
+	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
+	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
+	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */ 
+	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
+	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
+	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
+	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
+	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
+	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
+	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ 
+	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED);      /* disable Synchronius serial INT */
+	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
+	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
+	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
+	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
+	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
 	
 	if (CFG_USE_SIO_UART) {
-		write_mmcr_byte(SC520_UART1MAP,0);     /* disable internal UART1 INT */
-		write_mmcr_byte(SC520_UART2MAP,0);     /* disable internal UART2 INT */
-		write_mmcr_byte(SC520_GP3IMAP,11);     /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ 
-		write_mmcr_byte(SC520_GP4IMAP,12);     /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
+		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
+		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
+		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ 
+		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4);          /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
 	} else {
-		write_mmcr_byte(SC520_UART1MAP,12);    /* Set internal UART2 INT to IRQ4 */
-		write_mmcr_byte(SC520_UART2MAP,11);    /* Set internal UART2 INT to IRQ3 */
-		write_mmcr_byte(SC520_GP3IMAP,0);      /* disable GPIRQ3 (ISA IRQ3) */ 
-		write_mmcr_byte(SC520_GP4IMAP,0);      /* disable GPIRQ4 (ISA IRQ4) */
+		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);         /* Set internal UART2 INT to IRQ4 */
+		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);         /* Set internal UART2 INT to IRQ3 */
+		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ3 (ISA IRQ3) */ 
+		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ4 (ISA IRQ4) */
 	}
 	
-	write_mmcr_byte(SC520_GP5IMAP,13);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
-	write_mmcr_byte(SC520_GP6IMAP,21);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
-	write_mmcr_byte(SC520_GP7IMAP,22);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
-	write_mmcr_byte(SC520_GP8IMAP,3);              /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
-	write_mmcr_byte(SC520_GP9IMAP,4);              /* Set GPIRQ9 (ISA IRQ9) to IRQ9 */
-	write_mmcr_byte(SC520_GP10IMAP,9);             /* Set GPIRQ10 (ISA IRQ10) to IRQ10 */          
-	write_mmcr_word(SC520_PCIHOSTMAP,0x11f);       /* Map PCI hostbridge INT to NMI */
-	write_mmcr_word(SC520_ECCMAP,0x100);           /* Map SDRAM ECC failure INT to NMI */
+	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1);             /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
+	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
+	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
+	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
+	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8);             /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
+	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9);             /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
+	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11);            /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
+	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12);            /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14);            /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */          
+	
+	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);                /* Map PCI hostbridge INT to NMI */
+	write_mmcr_word(SC520_ECCMAP, 0x100);                    /* Map SDRAM ECC failure INT to NMI */
  
 }
 
+	
 /* PCI stuff */
 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
-	char pin;
-	int irq;
-	
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CFG_FIRST_PCI_IRQ,
+		CFG_SECOND_PCI_IRQ,
+		CFG_THIRD_PCI_IRQ,
+		CFG_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+	
+	char tmp_pin;	
+	int pin;
+	
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+	
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
 	
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
-	irq = pin-1;
 	
+       
+	/* map device number +  pin to a pin on the sc520 */
 	switch (PCI_DEV(dev)) {
 	case 20:
+		pin+=SC520_PCI_INTA;
 		break;
+		
 	case 19:
-		irq+=1;
+		pin+=SC520_PCI_INTB;
 		break;
+		
 	case 18:
-		irq+=2;
+		pin+=SC520_PCI_INTC;
 		break;
+		
 	case 17:
-		irq+=3;
+		pin+=SC520_PCI_INTD;
 		break;
+		
 	default: 
 		return;
 	}
 	
-	irq&=3; /* wrap around */
-	irq+=9; /* lowest IRQ is 9 */
+	pin&=3; /* wrap around */
 	
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, irq);
-#if 0	
-	printf("fixup_irq: device %d pin %c irq %d\n", 
-	       PCI_DEV(dev), 'A' + pin -1, irq);
-#endif
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */		
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { 
+			return;
+		}
+		next_irq_index++;
+	}
+
+	
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 
+					   sc520_pci_ints[pin]);
+	}
+	PRINTF("fixup_irq: device %d pin %c irq %d\n", 
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
 }
  
 static struct pci_controller sc520_cdp_hose = {
@@ -202,6 +255,7 @@
 	 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ 
 	
 		
+	
 	/* SRAM = GPCS3 128k @ d0000-effff*/
 	write_mmcr_long(SC520_PAR2,  0x4e00400d);		
 	
@@ -233,7 +287,192 @@
 
 }
 
+/* GPCS usage
+ * GPCS0       PIO27 (NMI)
+ * GPCS1       ROMCS1
+ * GPCS2       ROMCS2
+ * GPCS3       SRAMCS       PAR2
+ * GPCS4       unused       PAR3
+ * GPCS5       unused       PAR4
+ * GPCS6       IDE
+ * GPCS7       IDE
+ */
+
 
+/* par usage:
+ * PAR0   legacy_video
+ * PAR1   PCI ROM mapping
+ * PAR2   SRAM
+ * PAR3   IDE
+ * PAR4   IDE
+ * PAR5   legacy_video
+ * PAR6   legacy_video
+ * PAR7   legacy_video
+ * PAR8   legacy_video
+ * PAR9   legacy_video
+ * PAR10  legacy_video
+ * PAR11  ISAROM
+ * PAR12  BOOTCS
+ * PAR13  ROMCS1
+ * PAR14  ROMCS2
+ * PAR15  Port 0x680 LED display
+ */
+
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ * 
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size) 
+{
+	u32 par;
+	
+	PRINTF("isa_map_rom asked to map %d bytes at %x\n", 
+	       size, bus_addr);
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+	
+	PRINTF ("setting PAR11 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR11,  par);
+	
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	PRINTF("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
+		write_mmcr_long(SC520_PAR11, 0);
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+}
+
+#ifdef CONFIG_PCI
+#define PCI_ROM_TEMP_SPACE 0x10000
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address 
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size) 
+{
+	u32 par;
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+	
+	PRINTF ("setting PAR1 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR1,  par);
+	
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	PRINTF("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		write_mmcr_long(SC520_PAR1, 0);
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+	
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus. 
+ * After this function accesses to I/O ports 0x3b0-0x3bb and 
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ * 
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	write_mmcr_long(SC520_PAR0,  0x7200400a);
+	
+	/* forward all I/O accesses to PCI */
+	write_mmcr_byte(SC520_ADDDECCTL, 
+			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);	
+	
+	
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers 
+	 */
+	
+	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
+	write_mmcr_long(SC520_PAR5, 0x30ef0100);		
+	
+	/* IDE use 1f0-1f7 */
+	
+	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
+	write_mmcr_long(SC520_PAR6, 0x30ff01f8);		
+	
+	/* com2 use 2f8-2ff */
+	
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	write_mmcr_long(SC520_PAR7, 0x30af0300);		
+	
+	/* vga use 3b0-3bb */
+	
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	write_mmcr_long(SC520_PAR8, 0x300303bc);		
+	
+	/* vga use 3c0-3df */
+	
+	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
+	write_mmcr_long(SC520_PAR9, 0x301503e0);		
+	
+	/* ide use 3f6 */
+	
+	/* bring 0x3f7  back to ISA using PAR10 */
+	write_mmcr_long(SC520_PAR10, 0x300003f7);		
+	
+	/* com1 use 3f8-3ff */		
+
+	return 0;
+}
+#endif
 
 /*
  * Miscelaneous platform dependent initialisations
@@ -252,7 +491,6 @@
 		
 	/* enter debug mode after next reset (only if jumper is also set) */
 	write_mmcr_byte(SC520_RESCFG, 0x08);
-	
 	/* configure the software timer to 33.333MHz */
 	write_mmcr_byte(SC520_SWTMRCFG, 0);
 	gd->bus_clk = 33333000;
diff -urN -x CVS u-boot/board/sc520_cdp/sc520_cdp_asm16.S u-boot-i386/board/sc520_cdp/sc520_cdp_asm16.S
--- u-boot/board/sc520_cdp/sc520_cdp_asm16.S	Mon Nov 18 01:14:45 2002
+++ u-boot-i386/board/sc520_cdp/sc520_cdp_asm16.S	Wed Nov 20 14:16:00 2002
@@ -60,3 +60,25 @@
 	/* the return address is tored in bp */
 	jmp	*%bp
 	
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+realmode_reset:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax	
+	outl	%eax, %dx		
+	
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax		
+	movw	%ax, %ds		 
+		
+	/* issue software reset thorugh MMCR */
+	movl    $0xd72, %edi
+        movb	$0x01, %al
+        movb	%al, (%di)		
+
+1:	hlt
+	jmp	1
+	
diff -urN -x CVS u-boot/board/sc520_cdp/u-boot.lds u-boot-i386/board/sc520_cdp/u-boot.lds
--- u-boot/board/sc520_cdp/u-boot.lds	Mon Nov 18 01:14:45 2002
+++ u-boot-i386/board/sc520_cdp/u-boot.lds	Wed Nov 20 14:20:13 2002
@@ -27,7 +27,7 @@
 
 SECTIONS
 {	
-	. = 0x387e0000;                     /* Where bootcode in the flash is mapped */
+	. = 0x387c0000;                     /* Where bootcode in the flash is mapped */
 	.text  : { *(.text); }
 	
         . = ALIGN(4);
diff -urN -x CVS u-boot/board/sc520_spunk/Makefile u-boot-i386/board/sc520_spunk/Makefile
--- u-boot/board/sc520_spunk/Makefile	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/Makefile	Tue Apr 29 13:40:04 2003
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Daniel Engstr?m, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sc520_spunk.o flash.o ssi_eeprom.o
+SOBJS	:= sc520_spunk_asm.o sc520_spunk_asm16.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff -urN -x CVS u-boot/board/sc520_spunk/config.mk u-boot-i386/board/sc520_spunk/config.mk
--- u-boot/board/sc520_spunk/config.mk	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/config.mk	Fri Mar 28 08:48:28 2003
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Daniel Engstr?m, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+TEXT_BASE = 0x387c0000
diff -urN -x CVS u-boot/board/sc520_spunk/flash.c u-boot-i386/board/sc520_spunk/flash.c
--- u-boot/board/sc520_spunk/flash.c	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/flash.c	Thu Apr 24 11:32:54 2003
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, daniel@omicron.se
+ * 
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+ulong myflush(void);
+
+
+#define SC520_MAX_FLASH_BANKS  1
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANKSIZE   0x8000000
+
+#define I28F640J3A_SIZE        0x800000
+#define I28F640J3A_SECTORS     64
+
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _probe_flash(u32 addr, u32 bw)
+{
+	u32 result;
+	int reg1 = 0;
+	int reg2 = 0;
+	
+	/* First do an unlock cycle for the benefit of
+	 * devices that need it */
+
+	switch (bw) {
+		
+	 case 1:
+		*(volatile u8*)(addr+0x5555) = 0xaa;
+		*(volatile u8*)(addr+0x2aaa) = 0x55;
+		reg1 = 0x5555;
+		reg2 = 2;
+		break;
+		
+	 case 2:
+		*(volatile u16*)(addr+0xaaaa) = 0xaaaa;
+		*(volatile u16*)(addr+0x5554) = 0x5555;
+		reg1 = 0xaaaa;		
+		reg2 = 2;
+		break;
+		
+	 case 4:
+		*(volatile u32*)(addr+0x5554) = 0xaaaaaaaa;
+		*(volatile u32*)(addr+0xaaa8) = 0x55555555;
+		reg1 = 0x5554;
+		reg2 = 4;
+		break;
+	}
+	
+	/* Issue identification command */
+	*(volatile u8*)(addr + reg1) = 0x90;
+	
+	/* Read vendor */
+	result = *(volatile u8*)addr;
+	result <<= 16;
+	
+	/* Read device */
+	result |= *(volatile u8*)(addr+reg1);
+	
+	/* Return device to data mode */
+	*(volatile u32*)addr =  0xffffffff;
+	*(volatile u32*)(addr+reg1), 0xf0f0f0f0;  
+	
+	return result;
+}
+
+extern int _probe_flash_end;
+asm ("_probe_flash_end:\n"
+     ".long 0\n");
+
+static int identify_flash(unsigned address, int width)
+{
+#define PROBE_BUFFER_SIZE 256
+	int is;	
+	int device;
+	int vendor;	
+	int size;
+	unsigned res;
+	
+	unsigned char buffer[PROBE_BUFFER_SIZE];
+	u32 (*_probe_flash_ptr)(u32 a, u32 bw);
+	
+	size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; 
+	
+	if (size > PROBE_BUFFER_SIZE) {
+		printf("_probe_flash() routine too large (%d) %p - %p\n",
+		      size, &_probe_flash_end, _probe_flash);
+		return 0;
+	}
+	
+	memcpy(buffer, _probe_flash, size);
+	_probe_flash_ptr = (void*)buffer;
+	
+	is = disable_interrupts();
+	printf("calling flash_detect\n");
+	res = _probe_flash_ptr(address, width);
+	if (is) {
+		enable_interrupts();
+	}
+	
+	printf("_probe_flash(): %08x\n", res);
+	
+        vendor = res >> 16;
+	device = res & 0xffff;
+	
+	printf("vendor: %04x device %04x\n", vendor, device);
+		
+	return res;
+}
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+	
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		int sectsize = 0; 
+		if (i==0) {
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+			
+			flash_info[i].size = I28F640J3A_SIZE;
+			flash_info[i].sector_count = I28F640J3A_SECTORS;
+			sectsize = I28F640J3A_SIZE/I28F640J3A_SECTORS;
+		} 
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		default:
+			panic("configured to many flash banks!\n");
+		}
+		
+		identify_flash(flashbase, 2);
+		
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = sectsize;
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+	}
+	
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start-SC520_FLASH_BANK0_BASE,
+		      i386boot_end-SC520_FLASH_BANK0_BASE,
+		      &flash_info[0]);
+	
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf("INTEL: ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf("1x I28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+			printf("1x I28F640J3A (64Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
+			printf("1x I28F128J3A (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+		
+		break;
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD:   ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV640U & FLASH_TYPEMASK):
+			printf("1x AMD29LV641D (64Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+		
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	
+	
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	
+	done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	printf("sc520_spunk: flash_erase() not implemented yet\n");
+	return -1;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	printf("sc520_spunk: write_buff() not implemented yet\n");
+	return -1;
+}
+
diff -urN -x CVS u-boot/board/sc520_spunk/sc520_spunk.c u-boot-i386/board/sc520_spunk/sc520_spunk.c
--- u-boot/board/sc520_spunk/sc520_spunk.c	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/sc520_spunk.c	Mon Apr 28 13:43:42 2003
@@ -0,0 +1,558 @@
+/*
+ * 
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <ssi.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+
+
+/* ------------------------------------------------------------------------- */
+
+	
+/* 
+ * Theory:
+ * We first set up all IRQs to be non-pci, edge triggered,
+ * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets 
+ * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
+ * as needed. Whe choose the irqs to gram from a configurable list
+ * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
+ * such as 0 thngas will not work)
+ */
+
+static void irq_init(void)
+{
+	/* disable global interrupt mode */
+	write_mmcr_byte(SC520_PICICR, 0x40); 
+	
+	/* set all irqs to edge */
+	write_mmcr_byte(SC520_MPICMODE, 0x00);
+	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
+	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+	
+	/* active low polarity on PIC interrupt pins, 
+	 *  active high polarity on all other irq pins */
+	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+
+	/* set irq number mapping */
+	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */       
+	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
+	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
+	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */ 
+	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
+	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
+	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
+	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
+	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
+	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
+	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ 
+	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
+	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
+	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
+	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
+	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
+	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+	
+	write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
+	write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
+	
+	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
+	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
+	write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ 
+	write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
+	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
+	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
+	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
+	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
+	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
+	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
+	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */          
+	
+	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
+	write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
+ 
+}
+
+	
+/* PCI stuff */
+static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CFG_FIRST_PCI_IRQ,
+		CFG_SECOND_PCI_IRQ,
+		CFG_THIRD_PCI_IRQ,
+		CFG_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+	
+	char tmp_pin;	
+	int pin;
+	
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+	
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+	
+	
+       
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 6:  /* ETH0 */		  
+		pin+=SC520_PCI_INTA;
+		break;
+		
+	case 7:  /* ETH1 */
+		pin+=SC520_PCI_INTB;
+		break;
+		
+	case 8:  /* Crypto */
+		pin+=SC520_PCI_INTC;
+		break;
+		
+	case 9: /* PMC slot */
+		pin+=SC520_PCI_INTD;
+		break;
+		
+	case 10: /* PC-Card */
+		
+		if (version < 10) {			
+			pin+=SC520_PCI_INTD;
+		} else {
+			pin+=SC520_PCI_INTC;
+		}
+		break;
+		
+	default: 
+		return;
+	}
+	
+	pin&=3; /* wrap around */
+	
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */		
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { 
+			return;
+		}
+		next_irq_index++;
+	}
+
+	
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 
+					   sc520_pci_ints[pin]);
+	}
+#if 0	
+	printf("fixup_irq: device %d pin %c irq %d\n", 
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+#endif
+}
+
+
+static int pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *te)
+{
+	u32 io_base;
+	int res;
+	u32 temp;
+	
+	res = pciauto_config_device(hose, dev);
+	
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
+	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
+	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
+	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
+	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
+	
+	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */ 
+	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */ 
+	/* route MF0 to ~INT and MF3 to IRQ7 
+	 * reserve all others */
+	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); 
+	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
+	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
+	
+	if (te->device != 0xac56) {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
+		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
+	} else {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
+	}
+	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
+	
+	
+	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
+	io_base &= ~0xfL;
+	
+	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
+	writel(0, io_base+0x10);     /* CLKRUN default */
+	writel(0, io_base+0x20);     /* CLKRUN default */
+	
+	return res;
+}
+
+
+
+static struct pci_config_table pci_sc520_spunk_config_table[] = {
+	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, 
+	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, 
+	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
+};
+
+static struct pci_controller sc520_spunk_hose = {
+	fixup_irq: pci_sc520_spunk_fixup_irq,
+	config_table: pci_sc520_spunk_config_table
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_spunk_hose);
+}
+
+
+/* set up the ISA bus timing and system address mappings */
+static void bus_init(void)
+{
+	/* versions 
+	 * 0   Hyglo versions 0.95 and 0.96 (large baords)
+	 * ??  Hyglo version 0.97 (small board)
+	 * 10  Spunk board
+	 */
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version) {
+		/* set up the GP IO pins (for the Spunk board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x000f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0xc0);  		/* set the CS pin function reg */	
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+	} else {
+		/* set up the GP IO pins (for the Hyglo board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0, 0x1fff);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x003f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0, 0xe000);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0x00);  		/* set the CS pin function reg */	
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+	}
+	
+	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */    	
+	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
+	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
+	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
+	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
+        write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
+	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
+
+	write_mmcr_word(SC520_BOOTCSCTL, 0x0407);		/* set up timing of BOOTCS */ 
+	
+	/* adjust the memory map:
+	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
+	 * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
+	 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ 
+	
+		
+	
+	/* bootcs */
+	write_mmcr_long(SC520_PAR12, 0x8bffe800);		
+	
+	/* IDE0 = GPCS6 1f0-1f7 */
+	write_mmcr_long(SC520_PAR3,  0x380801f0);		
+
+	/* IDE1 = GPCS7 3f6 */
+	write_mmcr_long(SC520_PAR4,  0x3c0003f6);		
+
+	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */	
+
+	write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));	
+
+}
+
+
+
+/* par usage:
+ * PAR0   (legacy_video)
+ * PAR1   (PCI ROM mapping)
+ * PAR2 
+ * PAR3   IDE 
+ * PAR4   IDE
+ * PAR5   (legacy_video)
+ * PAR6 
+ * PAR7   (legacy_video)
+ * PAR8   (legacy_video)
+ * PAR9   (legacy_video)
+ * PAR10
+ * PAR11  (ISAROM)
+ * PAR12  BOOTCS
+ * PAR13
+ * PAR14
+ * PAR15
+ */
+
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ * 
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size) 
+{
+	u32 par;
+	
+	printf("isa_map_rom asked to map %d bytes at %x\n", 
+	       size, bus_addr);
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+	
+	printf ("setting PAR11 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR11,  par);
+	
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	printf("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
+		write_mmcr_long(SC520_PAR11, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+}
+
+#ifdef CONFIG_PCI
+#define PCI_ROM_TEMP_SPACE 0x10000
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address 
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size) 
+{
+	u32 par;
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+	
+	printf ("setting PAR1 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR1,  par);
+	
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	printf("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		write_mmcr_long(SC520_PAR1, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+	
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus. 
+ * After this function accesses to I/O ports 0x3b0-0x3bb and 
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ * 
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	write_mmcr_long(SC520_PAR0,  0x7200400a);
+	
+	/* forward all I/O accesses to PCI */
+	write_mmcr_byte(SC520_ADDDECCTL, 
+			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);	
+	
+	
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers 
+	 */
+	
+	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
+	write_mmcr_long(SC520_PAR5, 0x31f70100);		
+		
+	/* com2 use 2f8-2ff */
+	
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	write_mmcr_long(SC520_PAR7, 0x30af0300);		
+	
+	/* vga use 3b0-3bb */
+	
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	write_mmcr_long(SC520_PAR8, 0x300303bc);		
+	
+	/* vga use 3c0-3df */
+	
+	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
+	write_mmcr_long(SC520_PAR9, 0x301703e0);		
+		
+	/* com1 use 3f8-3ff */		
+
+	return 0;
+}
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	
+	init_sc520();	
+	bus_init();
+	irq_init();
+		
+	/* max drive current on SDRAM */
+	write_mmcr_word(SC520_DSCTL, 0x0100);
+		
+	/* enter debug mode after next reset (only if jumper is also set) */
+	write_mmcr_byte(SC520_RESCFG, 0x08);
+	/* configure the software timer to 33.000MHz */
+	write_mmcr_byte(SC520_SWTMRCFG, 1);
+	gd->bus_clk = 33000000;
+	
+	return 0;
+}
+
+int dram_init(void)
+{
+	init_sc520_dram();
+	return 0;
+}
+
+void show_boot_progress(int val)
+{
+ 	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version == 0) {
+		/* PIO31-PIO16 Data */
+		write_mmcr_word(SC520_PIODATA31_16,                                           
+				(read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
+		
+		/* PIO0-PIO15 Data */
+		write_mmcr_word(SC520_PIODATA15_0, 
+				(read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
+	} else {
+		/* newer boards use PIO4-PIO12 */
+		/* PIO0-PIO15 Data */
+#if 0		
+		val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3); 
+#else
+		val = (val & 0x007) | ((val & 0x07e) << 2); 
+#endif
+		write_mmcr_word(SC520_PIODATA15_0, 
+				(read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
+	}
+}
+
+
+int last_stage_init(void)
+{
+	
+	printf("Omicron Ceti SC520 Spunk revision %x\n", read_mmcr_byte(SC520_SYSINFO));
+	ssi_eeprom_probe(1);
+	printf("eeprom bytes %04x%04x\n", ssi_eeprom_read(1, 0), ssi_eeprom_read(1,1));
+	return 0;
+}
+
+void ssi_chip_select(int dev) 
+{
+
+	switch (dev) {
+	case 1:
+		write_mmcr_word(SC520_PIOSET15_0, 0x0100);
+		break;
+	case 2:
+		write_mmcr_word(SC520_PIOSET15_0, 0x0080);
+		break;
+		
+	case 0:
+	default:
+		write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
+	}
+		       
+}
diff -urN -x CVS u-boot/board/sc520_spunk/sc520_spunk_asm.S u-boot-i386/board/sc520_spunk/sc520_spunk_asm.S
--- u-boot/board/sc520_spunk/sc520_spunk_asm.S	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/sc520_spunk_asm.S	Wed Dec  4 13:53:55 2002
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* now setup the General purpose bus to give us access to the LEDs.
+ * We can then use the leds to display status information.
+ */ 
+
+sc520_cdp_registers:
+/* size    offset        value */
+.word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
+.word 2 ; .word 0xc08 ; .long 0x0001     /* GP CS offset */
+.word 2 ; .word 0xc09 ; .long 0x0003     /* GP CS width */
+.word 2 ; .word 0xc0a ; .long 0x0001     /* GP CS width */
+.word 2 ; .word 0xc0b ; .long 0x0003     /* GP RD pulse width */
+.word 2 ; .word 0xc0c ; .long 0x0001     /* GP RD offse */
+.word 2 ; .word 0xc0d ; .long 0x0003     /* GP WR pulse width */
+.word 2 ; .word 0xc0e ; .long 0x0001     /* GP WR offset */
+.word 2 ; .word 0xc2c ; .long 0x003f     /* GPIO directionreg 31-16 */
+.word 2 ; .word 0xc2a ; .long 0xe000     /* GPIO directionreg 15-0 */
+.word 2 ; .word 0xc22 ; .long 0xffc0     /* GPIO pin function 31-16 reg */
+.word 2 ; .word 0xc20 ; .long 0x1fff     /* GPIO pin function 15-0 reg */
+.word 0 ; .word 0x000 ; .long 0x00
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+        movl    $sc520_cdp_registers,%esi
+init_loop:	
+        movl    $0xfffef000,%edi     /* MMCR base to edi */					
+	movw	(%esi), %bx          /* load size to bx */
+	cmpw	$0, %bx              /* if size is 0 we're done */
+	je	done 
+	xorl	%edx,%edx
+	movw	2(%esi), %dx        /* load MMCR offset to dx */
+	addl	%edx, %edi          /* add offset to base in edi */
+	movl	4(%esi), %eax       /* load value in eax */
+	cmpw	$1, %bx
+	je	byte                 /* byte op? */
+	cmpw	$2, %bx
+	je	word                 /* word op? */
+	movl	%eax, (%edi)         /* must be long, then */
+	jmp	next
+byte:   movb    %al,(%edi)        
+	jmp	next
+word:	movw	%ax,(%edi)
+next:	addl	$8, %esi             /* advance esi */
+	jmp	init_loop
+
+	/* light all leds */
+done:   movl    $0xfffefc32,%edx 
+	movw    $0000,(%edx)              
+
+	jmp 	*%ebp		     /* return to caller */
+
+
+.globl __show_boot_progress
+__show_boot_progress:
+	movl    $0xfffefc32,%edx 
+	xorw    $0xffff, %ax 
+	movw    %ax,(%edx)              
+	jmp	*%ebp
+
diff -urN -x CVS u-boot/board/sc520_spunk/sc520_spunk_asm16.S u-boot-i386/board/sc520_spunk/sc520_spunk_asm16.S
--- u-boot/board/sc520_spunk/sc520_spunk_asm16.S	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/sc520_spunk_asm16.S	Wed Dec  4 13:48:52 2002
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax	
+	outl	%eax, %dx		
+	
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax		
+	movw	%ax, %ds		 
+		
+	/* Map the entire flash at 0x38000000  
+	 * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */
+	movl    $0xc0, %edi
+        movl	$0x8bfff800, %eax
+        movl	%eax, (%di)		
+
+	/* Disable SDRAM write buffer */
+	movw    $0x40,%di
+        xorw    %ax,%ax
+        movb    %al, (%di)              
+
+	/* Disabe MMCR alias */
+	movw	$0xfffc, %dx
+	movl	$0x000000cb, %eax	
+	outl	%eax, %dx		
+	
+	/* the return address is stored in bp */
+	jmp	*%bp
+	
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+realmode_reset:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax	
+	outl	%eax, %dx		
+	
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax		
+	movw	%ax, %ds		 
+		
+	/* issue software reset thorugh MMCR */
+	movl    $0xd72, %edi
+        movb	$0x01, %al
+        movb	%al, (%di)		
+
+1:	hlt
+	jmp	1
+	
diff -urN -x CVS u-boot/board/sc520_spunk/ssi_eeprom.c u-boot-i386/board/sc520_spunk/ssi_eeprom.c
--- u-boot/board/sc520_spunk/ssi_eeprom.c	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/ssi_eeprom.c	Fri Mar 28 08:48:28 2003
@@ -0,0 +1,159 @@
+
+#include <common.h>
+#include <ssi.h>
+
+/*
+ * Serial EEPROM opcodes, including start bit
+ */
+#define EEP_OPC_ERASE	0x7  /* 3-bit opcode */
+#define EEP_OPC_WRITE	0x5  /* 3-bit opcode */
+#define EEP_OPC_READ	        0x6  /* 3-bit opcode */
+
+#define EEP_OPC_ERASE_ALL	0x12 /* 5-bit opcode */
+#define EEP_OPC_ERASE_EN	0x13 /* 5-bit opcode */
+#define EEP_OPC_WRITE_ALL	0x11 /* 5-bit opcode */
+#define EEP_OPC_ERASE_DIS	0x10 /* 5-bit opcode */
+
+static int addrlen;
+
+static void ssi_eeprom_select(int dev)
+{
+	ssi_set_interface(2048, 0, 0, 0);
+	ssi_chip_select(0);
+	udelay(1);
+	ssi_chip_select(dev);
+	udelay(1);
+}
+
+static int ssi_eeprom_size(int dev)
+{
+	int x;
+	u16 res;
+		
+	ssi_eeprom_select(dev);
+	ssi_tx_byte(EEP_OPC_READ);
+	
+	res = ssi_txrx_byte(0) << 8;
+	res |= ssi_rx_byte();
+	for (x = 0; x < 16; x++) {
+		if (! (res & 0x8000)) {
+			break;
+		}
+		res <<= 1;
+	}
+	ssi_chip_select(0);
+	
+	return x;
+}
+
+int ssi_eeprom_erase_enable(int dev)
+{
+	ssi_eeprom_select(dev);
+	ssi_tx_byte(EEP_OPC_ERASE_EN);
+	ssi_tx_byte(0);
+	udelay(1);
+	ssi_chip_select(0);
+		
+	return 0;
+}
+
+int ssi_eeprom_erase_disable(int dev)
+{	
+	ssi_eeprom_select(dev);
+	ssi_tx_byte(EEP_OPC_ERASE_DIS);
+	ssi_tx_byte(0);
+	udelay(1);
+	ssi_chip_select(0);
+		
+	return 0;
+}
+
+
+u32 ssi_eeprom_read(int dev, int addr)
+{
+	u16 rcv;
+	u16 res;
+	int bits;
+	
+	ssi_eeprom_select(dev);
+	ssi_tx_byte((EEP_OPC_READ << 5) | ((addr >> (addrlen - 5)) & 0x1f));
+	rcv = ssi_txrx_byte(addr << (13 - addrlen));
+	res = rcv << (16 - addrlen);
+	bits = 4 + addrlen;
+	
+	while (bits>0) {
+		rcv = ssi_rx_byte();
+		if (bits > 7) {
+			res |= rcv << (bits - 8);
+		} else {
+			res |= rcv >> (8 - bits);
+		}
+		bits -= 8;
+	}
+	
+	ssi_chip_select(0);
+	
+	return res;
+}
+
+int ssi_eeprom_write(int dev, int addr, u32 data)
+{
+	u8 byte1=0;
+	u8 c2=0;
+	
+	ssi_eeprom_erase_enable(dev);
+	ssi_eeprom_select(dev);
+	
+	switch (addrlen) {
+	 case 6:
+		byte1 = EEP_OPC_WRITE >> 2;
+		c2 = (EEP_OPC_WRITE << 6)&0xc0;
+		c2 |= addr;
+		break;
+	 case 7:
+		byte1 = EEP_OPC_WRITE >> 1;
+		c2 = (EEP_OPC_WRITE << 7)&0x80;
+		c2 |= addr;
+		break;
+	 case 8:
+		byte1 = EEP_OPC_WRITE;
+		c2 = addr;
+		break;
+	 case 9:
+		byte1 = EEP_OPC_WRITE << 1;
+		byte1 |= addr >> 8;
+		c2 = addr & 0xff;
+		break;
+	 case 10:
+		byte1 = EEP_OPC_WRITE << 2;
+		byte1 |= addr >> 8;
+		c2 = addr & 0xff;
+		break;
+	 default:
+		printf("Unsupported number of address bits: %d\n", addrlen);
+		return -1;
+		
+	}
+	
+	ssi_tx_byte(byte1);
+	ssi_tx_byte(c2);
+	ssi_tx_byte(data >> 8);	
+	ssi_tx_byte(data & 0xff);
+	ssi_chip_select(0);	
+
+	ssi_eeprom_erase_disable(dev);
+
+	return 0;
+}
+
+
+int ssi_eeprom_probe(int dev)
+{
+	addrlen = ssi_eeprom_size(dev);
+	
+	if (addrlen < 6 || addrlen > 10) {
+		return -1;
+	}
+	return 0;
+}
+
diff -urN -x CVS u-boot/board/sc520_spunk/u-boot.lds u-boot-i386/board/sc520_spunk/u-boot.lds
--- u-boot/board/sc520_spunk/u-boot.lds	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/board/sc520_spunk/u-boot.lds	Fri Mar 28 08:48:28 2003
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{	
+	. = 0x387c0000;                     /* Where bootcode in the flash is mapped */
+	.text  : { *(.text); }
+	
+        . = ALIGN(4);
+        .rodata : { *(.rodata) }
+
+        . = 0x400000; 	                    /* Ram data segment to use */
+	_i386boot_romdata_dest = ABSOLUTE(.);
+        .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
+	_i386boot_romdata_start = LOADADDR(.data); 	
+
+        . = ALIGN(4);
+        .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
+	_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); 	
+
+
+        . = ALIGN(4);
+	_i386boot_bss_start = ABSOLUTE(.);
+        .bss : { *(.bss) }	
+	_i386boot_bss_size = SIZEOF(.bss);
+	
+	
+	/* 16bit realmode trampoline code */
+	.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) }
+    
+	_i386boot_realmode = LOADADDR(.realmode);
+	_i386boot_realmode_size = SIZEOF(.realmode);
+	
+	/* 16bit BIOS emulation code (just enough to boot Linux) */
+	.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
+    
+	_i386boot_bios = LOADADDR(.bios);
+	_i386boot_bios_size = SIZEOF(.bios);
+	
+
+	/* The load addresses below assumes that the flash
+	 * will be mapped so that 0x387f0000 == 0xffff0000
+	 * at reset time
+	 *
+	 * The fe00 and ff00 offsets of the start32 and start16 
+	 * segments are arbitrary, the just have to be mapped
+	 * at reset and the code have to fit.
+	 * The fff0 offset of reset is important, however.
+	 */
+	 
+	 
+	. = 0xfffffe00;
+	.start32 : AT (0x387ffe00) { *(.start32); } 
+	
+	. = 0xff00;
+	.start16 : AT (0x387fff00) { *(.start16); }  
+	
+	. = 0xfff0;
+	.reset : AT (0x387ffff0) { *(.reset); }  
+	_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
+}
diff -urN -x CVS u-boot/include/configs/sc520_cdp.h u-boot-i386/include/configs/sc520_cdp.h
--- u-boot/include/configs/sc520_cdp.h	Mon Nov 18 01:14:46 2002
+++ u-boot-i386/include/configs/sc520_cdp.h	Wed Apr 30 12:45:53 2003
@@ -63,13 +63,6 @@
 #define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)
 
 
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CFG_ENV_IS_NOWHERE 1
-#undef CFG_ENV_IS_IN_FLASH 
-#undef CFG_ENV_IS_IN_NVRAM 
-#undef CFG_ENV_IS_INEEPROM
-
 #define CONFIG_BAUDRATE		9600
 
 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET)
@@ -86,8 +79,6 @@
 #define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /*  */
 
 /*
  * Miscellaneous configurable options
@@ -104,7 +95,7 @@
 
 #undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 
-#define	CFG_LOAD_ADDR		0x38000000	/* default load address	*/
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
 
 #define	CFG_HZ			1024		/* incrementer freq: 1kHz */
 
@@ -117,27 +108,39 @@
  */
 #define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of DRAM */
 
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
 
+#if 0
 #define PHYS_FLASH_1		0x38000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE		0x00800000 /* 8 MB */
 
 #define CFG_FLASH_BASE		PHYS_FLASH_1
+#endif
 
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
 #define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
 
 /* timeout values are in ticks */
 #define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x7a0000)	/* Addr of Environment Sector	*/
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#undef CFG_ENV_IS_NOWHERE
+#define CFG_ENV_IS_IN_FLASH 1 
+#undef CFG_ENV_IS_IN_NVRAM 
+#undef CFG_ENV_IS_INEEPROM
+
+#define CFG_ENV_ADDR		(0x387a0000)	/* Addr of Environment Sector	*/
 #define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /*  */
+
 /*-----------------------------------------------------------------------
  * Device drivers
  */
@@ -146,19 +149,20 @@
 #define CONFIG_PCNET_79C973
 #define CONFIG_PCNET_79C975
 #define PCNET_HAS_PROM         1
+
 /************************************************************
  * IDE/ATA stuff
  ************************************************************/
-#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXBUS		1   /* max. 2 IDE busses	*/
 #define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
 #define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
-#define CFG_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
+//#define CFG_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
 #define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
 #define CFG_ATA_REG_OFFSET	0	/* reg offset */
 #define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+#define CFG_ATA_BASE_ADDR       0
 
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
 #undef	CONFIG_IDE_LED			/* no led for ide supported	*/
 #undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
 #undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
@@ -176,23 +180,13 @@
 #define CONFIG_ISO_PARTITION /* Experimental */
 
 /************************************************************
- * Keyboard support
+ * Video/Keyboard support
  ************************************************************/
-#define CONFIG_ISA_KEYBOARD
+#define CONFIG_VIDEO			/* To enable video controller support */
+#define CONFIG_I8042_KBD
+#define CFG_ISA_IO 0
+
 
-#if 0
-/************************************************************
- * Video support
- ************************************************************/
-#define CONFIG_VIDEO			/*To enable video controller support */
-#define CONFIG_VIDEO_CT69000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */
-#endif
 
 /************************************************************
  * RTC
@@ -206,5 +200,11 @@
 #define CONFIG_PCI                                /* include pci support */
 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW
+
+#define	CFG_FIRST_PCI_IRQ   10
+#define	CFG_SECOND_PCI_IRQ  9 
+#define CFG_THIRD_PCI_IRQ   11 
+#define	CFG_FORTH_PCI_IRQ   15
+
 
 #endif	/* __CONFIG_H */
diff -urN -x CVS u-boot/include/configs/sc520_spunk.h u-boot-i386/include/configs/sc520_spunk.h
--- u-boot/include/configs/sc520_spunk.h	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/include/configs/sc520_spunk.h	Tue Apr 29 15:32:14 2003
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_X86		1	/* This is a X86 CPU		*/
+
+#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */	
+#define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
+#define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
+
+/* define at most one of these */
+#undef CFG_SDRAM_CAS_LATENCY_2T
+#define CFG_SDRAM_CAS_LATENCY_3T
+
+#define CFG_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
+#define CFG_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
+#undef  CFG_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
+#undef  CFG_TIMER_SC520                 /* use SC520 swtimers */
+#define CFG_TIMER_GENERIC       1       /* use the i8254 PIT timers */
+#undef  CFG_TIMER_TSC                   /* use the Pentium TSC timers */
+
+#define CFG_STACK_SIZE          0x8000  /* Size of bootloader stack */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+#define CONFIG_LAST_STAGE_INIT    1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)
+
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	15
+#define CONFIG_BOOTARGS    	"root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot) "
+#define CONFIG_BOOTCOMMAND	"setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm" 
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1024		/* incrementer freq: 1kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of DRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#undef CFG_ENV_IS_NOWHERE
+#define CFG_ENV_IS_IN_FLASH 1 
+#undef CFG_ENV_IS_IN_NVRAM 
+#undef CFG_ENV_IS_INEEPROM
+
+#define CFG_ENV_ADDR		(0x387a0000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /*  */
+
+/*-----------------------------------------------------------------------
+ * Device drivers
+ */
+#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
+#define CONFIG_EEPRO100
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CFG_ATA_BASE_ADDR       0
+#define CFG_ATA_IDE0_OFFSET	0x01f0	/* ide0 offset */
+#define CFG_ATA_IDE1_OFFSET	0xe000	/* ide1 offset */
+#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
+#define CFG_ATA_REG_OFFSET	0	/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+
+#define CFG_FISRT_PCMCIA_BUS    1
+
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
+#undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
+
+#define CONFIG_IDE_TI_CARDBUS
+#define CFG_PCMCIA_CIS_WIN          0x27f00000
+#define CFG_PCMCIA_CIS_WIN_SIZE     0x00100000
+#define CFG_PCMCIA_IO_WIN           0xe000
+#define CFG_PCMCIA_IO_WIN_SIZE      16
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+
+
+
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW
+
+#define	CFG_FIRST_PCI_IRQ   9
+#define	CFG_SECOND_PCI_IRQ  10 
+#define CFG_THIRD_PCI_IRQ   11 
+#define	CFG_FORTH_PCI_IRQ   12
+
+
+#endif	/* __CONFIG_H */
diff -urN -x CVS u-boot/include/configs/sc520_spunk_rel.h u-boot-i386/include/configs/sc520_spunk_rel.h
--- u-boot/include/configs/sc520_spunk_rel.h	Thu Jan  1 01:00:00 1970
+++ u-boot-i386/include/configs/sc520_spunk_rel.h	Wed Apr 30 14:14:05 2003
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _outer_config
+#define _outer_config
+
+#include "sc520_spunk.h"
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	"fsload boot/vmlinuz ; bootm" 
+
+#endif
