This is a cleaned up version of the U-Boot port provided with the BSP for the Freescale COM Express P2020 evaluation kit.
This board is booted from SD card or SPI flash by using the Freescale On-Chip ROM to load U-Boot into L2 SRAM. U-Boot configures and initializes the DDR SDRAM using the SPD on the module.
The SPD on the 2GB DDR3 DIMM shipped with this evaluation kit has an invalid value (0x08) in the module_type field (eeprom address 0x03). Therefore, a workaround patch was added to the SPD decoder to assume an unregistered DIMM in this case. Other suggestions are welcome.
Changes v3 -> v4: - address review comments - boot via L2 SRAM (just like P2020DS) - use SPD EEPROM to configure DDR SDRAM
Changes v2 -> v3: - re-enable CCSR relocation
Changes v1 -> v2: - fix checkpatch warnings - remove references to NAND (this board lacks NAND) - disable CCSR relocation
Ira W. Snyder (3): mpc85xx: support board-specific reset function mpc8xxx: assume unregistered DIMM for invalid SPD module_type mpc85xx: support for Freescale COM Express P2020
MAINTAINERS | 4 + arch/powerpc/cpu/mpc85xx/cpu.c | 17 +- arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 7 +- arch/powerpc/include/asm/immap_85xx.h | 1 + board/freescale/p2020come/Makefile | 46 ++ board/freescale/p2020come/ddr.c | 45 ++ board/freescale/p2020come/law.c | 39 ++ board/freescale/p2020come/p2020come.c | 287 +++++++++++ board/freescale/p2020come/tlb.c | 99 ++++ boards.cfg | 2 + include/configs/P2020COME.h | 576 +++++++++++++++++++++++ 11 files changed, 1118 insertions(+), 5 deletions(-) create mode 100644 board/freescale/p2020come/Makefile create mode 100644 board/freescale/p2020come/ddr.c create mode 100644 board/freescale/p2020come/law.c create mode 100644 board/freescale/p2020come/p2020come.c create mode 100644 board/freescale/p2020come/tlb.c create mode 100644 include/configs/P2020COME.h