On June 17, 2024 thus sayeth Emanuele Ghidoli:
From: Emanuele Ghidoli emanuele.ghidoli@toradex.com
MCU_CLKOUT0 output can be driven by two different clock inputs: one at 25 MHz and another at 50 MHz. Currently, the 25 MHz input clock is not selectable due to a duplication of the 50 MHz clock input in the mux configuration. This commit corrects the parent clock mux configuration, making the 25 MHz input clock selectable.
Signed-off-by: Emanuele Ghidoli emanuele.ghidoli@toradex.com
arch/arm/mach-k3/r5/j784s4/clk-data.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Nice catch!
Reviewed-by: Bryan Brattlof bb@ti.com
~Bryan
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index feaa13ee266b..793bcac93245 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -134,7 +134,7 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = {
static const char * const mcu_clkout_mux_out0_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout0_clk",
- "hsdiv4_16fft_mcu_2_hsdivout0_clk",
- "hsdiv4_16fft_mcu_2_hsdivout1_clk",
};
static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { @@ -338,7 +338,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 174, "mcu_clkout_mux_out0"), DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
- DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
- DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
-- 2.34.1