On Sep 29, 2010, at 12:31 PM, Haiying.Wang@freescale.com Haiying.Wang@freescale.com wrote:
From: Haiying Wang Haiying.Wang@freescale.com
The original code maps boot flash as non-cacheable region. When calling relocate_code in flash to copy u-boot from flash to ddr, every loop copy command is read from flash. The flash read speed will be the bottleneck, which consuming long time to do this operation. To resovle this, map the boot flash as write-through cache via tlb. And set tlb to remap the flash after code executing in ddr, to confirm flash erase operation properly done.
Signed-off-by: Kai.Jiang Kai.Jiang@freescale.com
board/freescale/mpc8569mds/mpc8569mds.c | 25 +++++++++++++++++++++++++ board/freescale/mpc8569mds/tlb.c | 15 ++++++++++----- include/configs/MPC8569MDS.h | 3 ++- 3 files changed, 37 insertions(+), 6 deletions(-)
applied to 85xx
- k