On Fri, Sep 23, 2022 at 08:07:36PM +0200, Michael Trimarchi wrote:
The max size is defined at architectural level
Signed-off-by: Michael Trimarchi michael@amarulasolutions.com
configs/evb-px30_defconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 240a044b2a..4f88879e18 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
All of the PX30 boards are wrong, so we should fix them all at once. And a sanity check on the rest of the rockchip boards is in order too. Can you please do this? Or do you want me to?