Signed-off-by: Zhang Wei wei.zhang@freescale.com --- include/asm-ppc/immap_85xx.h | 169 +--------------- include/asm-ppc/immap_86xx.h | 232 +--------------------- include/asm-ppc/immap_fsl_rio.h | 426 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 428 insertions(+), 399 deletions(-) create mode 100644 include/asm-ppc/immap_fsl_rio.h
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index d769d70..7d8522b 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -13,6 +13,7 @@
#include <asm/types.h> #include <asm/fsl_i2c.h> +#include <asm/immap_fsl_rio.h>
/* * Local-Access Registers and ECM Registers(0x0000-0x2000) @@ -1353,174 +1354,6 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif
-/* - * RapidIO Registers(0xc_0000-0xe_0000) - */ -typedef struct ccsr_rio { - uint didcar; /* 0xc0000 - Device Identity Capability Register */ - uint dicar; /* 0xc0004 - Device Information Capability Register */ - uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ - uint aicar; /* 0xc000c - Assembly Information Capability Register */ - uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ - uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ - uint socar; /* 0xc0018 - Source Operations Capability Register */ - uint docar; /* 0xc001c - Destination Operations Capability Register */ - char res1[32]; - uint msr; /* 0xc0040 - Mailbox Command And Status Register */ - uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ - char res2[4]; - uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ - char res3[12]; - uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ - uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ - char res4[4]; - uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ - uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ - char res5[144]; - uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ - char res6[28]; - uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ - uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ - char res7[20]; - uint pgccsr; /* 0xc013c - Port General Command and Status Register */ - uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ - uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ - uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ - char res8[12]; - uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ - uint pccsr; /* 0xc015c - Port Control Command and Status Register */ - char res9[65184]; - uint cr; /* 0xd0000 - Port Control Command and Status Register */ - char res10[12]; - uint pcr; /* 0xd0010 - Port Configuration Register */ - uint peir; /* 0xd0014 - Port Error Injection Register */ - char res11[3048]; - uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ - char res12[12]; - uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ - char res13[12]; - uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ - char res14[4]; - uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ - char res15[4]; - uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ - char res16[12]; - uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ - char res17[4]; - uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ - char res18[4]; - uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ - char res19[12]; - uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ - char res20[4]; - uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ - char res21[4]; - uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ - char res22[12]; - uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ - char res23[4]; - uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ - char res24[4]; - uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ - char res25[12]; - uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ - char res26[4]; - uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ - char res27[4]; - uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ - char res28[12]; - uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ - char res29[4]; - uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ - char res30[4]; - uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ - char res31[12]; - uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ - char res32[4]; - uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ - char res33[4]; - uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ - char res34[12]; - uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ - char res35[4]; - uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ - char res36[4]; - uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ - char res37[76]; - uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ - char res38[4]; - uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ - char res39[4]; - uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ - char res40[12]; - uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ - char res41[4]; - uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ - char res42[4]; - uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ - char res43[12]; - uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ - char res44[4]; - uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ - char res45[4]; - uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ - char res46[12]; - uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ - char res47[4]; - uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ - char res48[4]; - uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ - char res49[12]; - uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ - char res50[12]; - uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ - char res51[12]; - uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ - uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ - uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ - uint pecr; /* 0xd0e0c - Port Error Control Register */ - uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ - uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ - uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ - char res52[4]; - uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ - char res53[4]; - uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ - uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ - char res54[464]; - uint omr; /* 0xd1000 - Outbound Mode Register */ - uint osr; /* 0xd1004 - Outbound Status Register */ - uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ - uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */ - uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */ - uint osar; /* 0xd1014 - Outbound Unit Source Address Register */ - uint odpr; /* 0xd1018 - Outbound Destination Port Register */ - uint odatr; /* 0xd101c - Outbound Destination Attributes Register */ - uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */ - uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ - uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */ - char res55[52]; - uint imr; /* 0xd1060 - Outbound Mode Register */ - uint isr; /* 0xd1064 - Inbound Status Register */ - uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ - uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */ - uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */ - uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */ - char res56[1000]; - uint dmr; /* 0xd1460 - Doorbell Mode Register */ - uint dsr; /* 0xd1464 - Doorbell Status Register */ - uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */ - uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */ - uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */ - uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */ - char res57[104]; - uint pwmr; /* 0xd14e0 - Port-Write Mode Register */ - uint pwsr; /* 0xd14e4 - Port-Write Status Register */ - uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */ - uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */ - char res58[60176]; -} ccsr_rio_t; - /* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */ typedef struct par_io { uint cpodr; /* 0x100 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 169725b..dfcd61a 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -12,6 +12,7 @@
#include <asm/types.h> #include <asm/fsl_i2c.h> +#include <asm/immap_fsl_rio.h>
/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ typedef struct ccsr_local_mcm { @@ -1020,237 +1021,6 @@ typedef struct ccsr_pic { char res158[3916]; } ccsr_pic_t;
-/* RapidIO Registers(0xc_0000-0xe_0000) */ - -typedef struct ccsr_rio { - uint didcar; /* 0xc0000 - Device Identity Capability Register */ - uint dicar; /* 0xc0004 - Device Information Capability Register */ - uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ - uint aicar; /* 0xc000c - Assembly Information Capability Register */ - uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ - uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ - uint socar; /* 0xc0018 - Source Operations Capability Register */ - uint docar; /* 0xc001c - Destination Operations Capability Register */ - char res1[32]; - uint msr; /* 0xc0040 - Mailbox Command And Status Register */ - uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ - char res2[4]; - uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ - char res3[12]; - uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ - uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ - char res4[4]; - uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ - uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ - char res5[144]; - uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ - char res6[28]; - uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ - uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ - char res7[20]; - uint pgccsr; /* 0xc013c - Port General Command and Status Register */ - uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ - uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ - uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ - char res8[12]; - uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ - uint pccsr; /* 0xc015c - Port Control Command and Status Register */ - char res9[1184]; - uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ - char res10[4]; - uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ - uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ - char res11[4]; - uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ - uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ - uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ - char res12[32]; - uint edcsr; /* 0xc0640 - Port 0 error detect status register */ - uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ - uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ - uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ - uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ - uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ - uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ - char res13[12]; - uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ - uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ - char res14[63892]; - uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ - char res15[12]; - uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ - char res16[12]; - uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ - char res17[92]; - uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ - char res18[124]; - uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ - char res19[28]; - uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ - char res20[12]; - uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ - char res21[12]; - uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ - char res22[20]; - uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ - char res23[4]; - uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ - char res24[2716]; - uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ - uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ - char res25[8]; - uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ - char res26[12]; - uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ - uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ - uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ - char res27[4]; - uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ - uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ - uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ - uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ - uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ - uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ - uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ - char res28[4]; - uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ - uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ - uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ - uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ - uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ - uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ - uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ - char res29[4]; - uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ - uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ - uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ - uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ - uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ - uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ - uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ - char res30[4]; - uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ - uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ - uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ - uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ - uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ - uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ - uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ - char res31[4]; - uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ - uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ - uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ - uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ - uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ - uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ - uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ - char res32[4]; - uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ - uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ - uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ - uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ - uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ - uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ - uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ - char res33[4]; - uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ - uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ - uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ - uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ - uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ - uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ - uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ - char res34[4]; - uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ - uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ - uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ - uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ - char res35[64]; - uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ - uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ - char res36[4]; - uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ - char res37[12]; - uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ - char res38[4]; - uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ - char res39[4]; - uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ - char res40[12]; - uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ - char res41[4]; - uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ - char res42[4]; - uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ - char res43[12]; - uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ - char res44[4]; - uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ - char res45[4]; - uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ - char res46[12]; - uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ - char res47[12]; - uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ - char res48[12]; - uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ - uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ - uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ - uint pecr; /* 0xd0e0c - Port Error Control Register */ - uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ - uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ - uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ - char res49[4]; - uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ - char res50[4]; - uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ - uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ - char res51[8656]; - uint omr; /* 0xd3000 - Outbound Mode Register */ - uint osr; /* 0xd3004 - Outbound Status Register */ - uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ - uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ - uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ - uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ - uint odpr; /* 0xd3018 - Outbound Destination Port Register */ - uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ - uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ - uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ - uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ - uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ - uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ - uint omlr; /* 0xd3034 - Outbound Multicast List Register */ - char res52[40]; - uint imr; /* 0xd3060 - Outbound Mode Register */ - uint isr; /* 0xd3064 - Inbound Status Register */ - uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ - uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ - uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ - uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ - uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ - char res53[900]; - uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ - uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ - char res54[16]; - uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ - uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ - char res55[12]; - uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ - char res56[48]; - uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ - uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ - uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ - uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ - uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ - uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ - uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ - char res57[100]; - uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ - uint pwsr; /* 0xd34e4 - Port-Write Status Register */ - uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ - uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ - char res58[51984]; -} ccsr_rio_t;
/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ typedef struct ccsr_gur { diff --git a/include/asm-ppc/immap_fsl_rio.h b/include/asm-ppc/immap_fsl_rio.h new file mode 100644 index 0000000..d2aca83 --- /dev/null +++ b/include/asm-ppc/immap_fsl_rio.h @@ -0,0 +1,426 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_PPC_IMMAP_FSL_RIO_H_ +#define __ASM_PPC_IMMAP_FSL_RIO_H_ + +#undef FSL_RIO_IP_V1 +#undef FSL_RIO_IP_V2 + +#if defined(CONFIG_MPC8540) | defined(CONFIG_MPC8560) +#define FSL_RIO_IP_V1 +#else +#define FSL_RIO_IP_V2 +#endif + +#ifdef FSL_RIO_IP_V1 + +/* RapidIO Register for IP version 1 */ +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[65184]; + uint cr; /* 0xd0000 - Port Control Command and Status Register */ + char res10[12]; + uint pcr; /* 0xd0010 - Port Configuration Register */ + uint peir; /* 0xd0014 - Port Error Injection Register */ + char res11[3048]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + char res12[12]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res13[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + char res14[4]; + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res15[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + char res16[12]; + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + char res17[4]; + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res18[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + char res19[12]; + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + char res20[4]; + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res21[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + char res22[12]; + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + char res23[4]; + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res24[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + char res25[12]; + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + char res26[4]; + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res27[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + char res28[12]; + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + char res29[4]; + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res30[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + char res31[12]; + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + char res32[4]; + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + char res34[12]; + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + char res35[4]; + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res36[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + char res37[76]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + char res38[4]; + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res39[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res40[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res41[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res42[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res43[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res44[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res45[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res46[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res47[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res48[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res49[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res50[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res51[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res52[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res53[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res54[464]; + uint omr; /* 0xd1000 - Outbound Mode Register */ + uint osr; /* 0xd1004 - Outbound Status Register */ + uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd1014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd1018 - Outbound Destination Port Register */ + uint odatr; /* 0xd101c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */ + char res55[52]; + uint imr; /* 0xd1060 - Outbound Mode Register */ + uint isr; /* 0xd1064 - Inbound Status Register */ + uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */ + char res56[1000]; + uint dmr; /* 0xd1460 - Doorbell Mode Register */ + uint dsr; /* 0xd1464 - Doorbell Status Register */ + uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */ + uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */ + uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */ + uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */ + char res57[104]; + uint pwmr; /* 0xd14e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd14e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */ + char res58[60176]; +} ccsr_rio_t; + +#elif defined(FSL_RIO_IP_V2) + +/* RapidIO Register for IP version 2 */ +typedef struct ccsr_rio { + uint didcar; /* 0xc0000 - Device Identity Capability Register */ + uint dicar; /* 0xc0004 - Device Information Capability Register */ + uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ + uint aicar; /* 0xc000c - Assembly Information Capability Register */ + uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ + uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ + uint socar; /* 0xc0018 - Source Operations Capability Register */ + uint docar; /* 0xc001c - Destination Operations Capability Register */ + char res1[32]; + uint msr; /* 0xc0040 - Mailbox Command And Status Register */ + uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ + char res2[4]; + uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ + char res3[12]; + uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ + uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ + char res4[4]; + uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ + uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ + char res5[144]; + uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ + char res6[28]; + uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ + uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ + char res7[20]; + uint pgccsr; /* 0xc013c - Port General Command and Status Register */ + uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ + uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ + uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ + char res8[12]; + uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ + uint pccsr; /* 0xc015c - Port Control Command and Status Register */ + char res9[1184]; + uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ + char res10[4]; + uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ + uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ + char res11[4]; + uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ + uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ + uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ + char res12[32]; + uint edcsr; /* 0xc0640 - Port 0 error detect status register */ + uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ + uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ + uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ + uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ + uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ + uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ + char res13[12]; + uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ + uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ + char res14[63892]; + uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ + char res15[8]; + uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ + char res16[12]; + uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ + char res17[92]; + uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ + char res18[124]; + uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ + char res19[28]; + uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ + char res20[12]; + uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ + char res21[12]; + uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ + char res22[20]; + uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ + char res23[4]; + uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ + char res24[2716]; + uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ + uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ + char res25[8]; + uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + char res26[12]; + uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ + uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ + uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ + char res27[4]; + uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ + uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ + uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ + uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ + uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ + uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ + char res28[4]; + uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ + uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ + uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ + uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ + uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ + uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ + char res29[4]; + uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ + uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ + uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ + uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ + uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ + uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ + char res30[4]; + uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ + uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ + uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ + uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ + uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ + uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ + char res31[4]; + uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ + uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ + uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ + uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ + uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ + uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ + char res32[4]; + uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ + uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ + uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ + uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ + uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ + uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ + char res33[4]; + uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ + uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ + uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ + uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ + uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ + uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ + char res34[4]; + uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ + uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ + uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ + char res35[64]; + uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ + char res35a[4]; + uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ + char res36[4]; + uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + char res37[12]; + uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ + char res38[4]; + uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ + char res39[4]; + uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ + char res40[12]; + uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ + char res41[4]; + uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ + char res42[4]; + uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ + char res43[12]; + uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ + char res44[4]; + uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ + char res45[4]; + uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ + char res46[12]; + uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ + char res47[12]; + uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + char res48[12]; + uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ + uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ + uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ + uint pecr; /* 0xd0e0c - Port Error Control Register */ + uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ + uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + char res49[4]; + uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + char res50[4]; + uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ + char res51[8656]; + uint omr; /* 0xd3000 - Outbound Mode Register */ + uint osr; /* 0xd3004 - Outbound Status Register */ + uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ + uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ + uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ + uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ + uint odpr; /* 0xd3018 - Outbound Destination Port Register */ + uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ + uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ + uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ + uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ + uint omlr; /* 0xd3034 - Outbound Multicast List Register */ + char res52[40]; + uint imr; /* 0xd3060 - Outbound Mode Register */ + uint isr; /* 0xd3064 - Inbound Status Register */ + uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ + uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ + uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ + uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ + uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ + char res53[900]; + uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + char res54[16]; + uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ + uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ + char res55[12]; + uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ + char res56[48]; + uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ + uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ + uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ + uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ + uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ + char res57[100]; + uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ + uint pwsr; /* 0xd34e4 - Port-Write Status Register */ + uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ + uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + char res58[51984]; +} ccsr_rio_t; + +#endif +#endif /* __ASM_PPC_IMMAP_FSL_RIO_H_ */