-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 03 January 2020 20:22 To: Pragnesh Patel pragnesh.patel@sifive.com Cc: U-Boot Mailing List u-boot@lists.denx.de Subject: Re: [PATCH 2/3] riscv: Add FU540 specific includes
Hi Pragnesh,
On Tue, Dec 31, 2019 at 10:00 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:
Added headers needed by upcoming SPL support of FU540.
This headers are leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com
arch/riscv/include/asm/arch-fu540/cache.h | 43 ++++++++++++ arch/riscv/include/asm/arch-fu540/clint.h | 20 ++++++ arch/riscv/include/asm/arch-fu540/i2c.h | 48 +++++++++++++ arch/riscv/include/asm/arch-fu540/otp.h | 80 +++++++++++++++++++++ arch/riscv/include/asm/arch-fu540/spi.h | 86 +++++++++++++++++++++++ arch/riscv/include/asm/arch-fu540/uart.h | 35 +++++++++ 6 files changed, 312 insertions(+) create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h create mode 100644 arch/riscv/include/asm/arch-fu540/clint.h create mode 100644 arch/riscv/include/asm/arch-fu540/i2c.h create mode 100644 arch/riscv/include/asm/arch-fu540/otp.h create mode 100644 arch/riscv/include/asm/arch-fu540/spi.h create mode 100644 arch/riscv/include/asm/arch-fu540/uart.h
diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h new file mode 100644 index 0000000000..9043779650 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/cache.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019 SiFive, Inc.
- Authors:
- Pragnesh Patel pragnesh.patel@sifive.com
- Troy Benjegerdes troy.benjegerdes@sifive.com
- */
+#ifndef _CACHE_FU540_H +#define _CACHE_FU540_H
+/* Register offsets */ +#define CCACHE_INFO 0x000 +#define CCACHE_ENABLE 0x008 +#define CCACHE_INJECT 0x040 +#define CCACHE_META_FIX 0x100 +#define CCACHE_DATA_FIX 0x140 +#define CCACHE_DATA_FAIL 0x160 +#define CCACHE_FLUSH64 0x200 +#define CCACHE_FLUSH32 0x240 +#define CCACHE_WAYS 0x800
+/* Bytes inside the INFO field */ +#define CCACHE_INFO_BANKS 0 +#define CCACHE_INFO_WAYS 1 +#define CCACHE_INFO_LG_SETS 2 +#define CCACHE_INFO_LG_BLOCKBYTES 3
+/* INJECT types */ +#define CCACHE_ECC_TOGGLE_DATA 0x00000 #define +CCACHE_ECC_TOGGLE_META 0x10000
+/* Offsets per FIX/FAIL */ +#define CCACHE_ECC_ADDR 0x0 +#define CCACHE_ECC_COUNT 0x8
+/* Interrupt Number offsets from Base */ +#define CCACHE_INT_META_FIX 0 +#define CCACHE_INT_DATA_FIX 1 +#define CCACHE_INT_DATA_FAIL 2
+#endif /* _CACHE_FU540_H */ diff --git a/arch/riscv/include/asm/arch-fu540/clint.h b/arch/riscv/include/asm/arch-fu540/clint.h new file mode 100644 index 0000000000..f740f30f2d --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/clint.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019 SiFive, Inc.
- Authors:
- Pragnesh Patel pragnesh.patel@sifive.com
- Troy Benjegerdes troy.benjegerdes@sifive.com
- */
+#ifndef _CLINT_FU540_H +#define _CLINT_FU540_H
+#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8
nits: please have the value indented
I will update this in v2, thanks for the review.
+#endif /* _CLINT_FU540_H */ diff --git a/arch/riscv/include/asm/arch-fu540/i2c.h b/arch/riscv/include/asm/arch-fu540/i2c.h new file mode 100644 index 0000000000..66cc3edd94 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/i2c.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019 SiFive, Inc.
- Authors:
- Pragnesh Patel pragnesh.patel@sifive.com
- Troy Benjegerdes troy.benjegerdes@sifive.com
- */
+#ifndef _I2C_FU540_H +#define _I2C_FU540_H
+// CHECK: word vs byte alignment +// OC I2C Linux driver defines registers w/o alignment: +// +http://lxr.free-electrons.com/source/drivers/i2c/busses/i2c-ocores.c? +v=4.6#L46 +// +// However, register accessor functions use reg_shift value // +http://lxr.free-electrons.com/source/drivers/i2c/busses/i2c-ocores.c? +v=4.6#L80 +// which is platform specific: +// +http://lxr.free-electrons.com/source/drivers/i2c/busses/i2c-ocores.c? +v=4.6#L346
nits: please use /* */ for the comment format
Update in v2.
+#define I2C_PRESCALER_LO (0x00) +#define I2C_PRESCALER_HI (0x04) +#define I2C_CONTROL (0x08) +#define I2C_DATA (0x0C) +#define I2C_CMD (0x10) /* write only */ +#define I2C_STATUS (0x10) /* read only, same address as I2C_CMD */
+// I2C_CONTROL register +#define I2C_CONTROL_CORE_EN(x) (((x) & 0x1) << 7) +#define I2C_CONTROL_INT_EN(x) (((x) & 0x1) << 6)
+// I2C_CMD register +#define I2C_CMD_START(x) (((x) & 0x1) << 7) +#define I2C_CMD_STOP(x) (((x) & 0x1) << 6) +#define I2C_CMD_READ(x) (((x) & 0x1) << 5) +#define I2C_CMD_WRITE(x) (((x) & 0x1) << 4) +#define I2C_CMD_NACK(x) (((x) & 0x1) << 3) +#define I2C_CMD_IRQ_ACK(x) (((x) & 0x1))
+// I2C_STATUS register +#define I2C_STATUS_RECEIVED_NACK(x) (((x) & 0x80) >> 7) +#define I2C_STATUS_BUSY(x) (((x) & 0x40) >> 6) +#define I2C_STATUS_ARB_LOST(x) (((x) & 0x20) >> 5) +#define I2C_STATUS_TRS_INPROGRESS(x) (((x) & 0x02) >> 1) +#define I2C_STATUS_IRQ_FLAG(x) (((x) & 0x01))
+#endif /* _I2C_FU540_H */ diff --git a/arch/riscv/include/asm/arch-fu540/otp.h b/arch/riscv/include/asm/arch-fu540/otp.h new file mode 100644 index 0000000000..588e525765 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/otp.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019 SiFive, Inc.
- Authors:
- Pragnesh Patel pragnesh.patel@sifive.com
- Troy Benjegerdes troy.benjegerdes@sifive.com
- */
+#ifndef _OTP_FU540_H +#define _OTP_FU540_H
+/* Register offsets */
+#define EMEMORYOTP_PA 0x00 +#define EMEMORYOTP_PAIO 0x04 +#define EMEMORYOTP_PAS 0x08 +#define EMEMORYOTP_PCE 0x0C +#define EMEMORYOTP_PCLK 0x10 +#define EMEMORYOTP_PDIN 0x14 +#define EMEMORYOTP_PDOUT 0x18 +#define EMEMORYOTP_PDSTB 0x1C +#define EMEMORYOTP_PPROG 0x20 +#define EMEMORYOTP_PTC 0x24 +#define EMEMORYOTP_PTM 0x28 +#define EMEMORYOTP_PTM_REP 0x2C +#define EMEMORYOTP_PTR 0x30 +#define EMEMORYOTP_PTRIM 0x34 +#define EMEMORYOTP_PWE 0x38
+/* Timing delays (in us)
- MIN indicates that there is no maximum.
- TYP indicates that there is a maximum
- that should not be exceeded.
- When the minimums are < 1us, I just put 1us.
- */
+#define EMEMORYOTP_MIN_TVDS 1 +#define EMEMORYOTP_MIN_TSAS 2 +#define EMEMORYOTP_MIN_TTAS 50 +#define EMEMORYOTP_MIN_TTAH 1 +#define EMEMORYOTP_MIN_TASH 1 +#define EMEMORYOTP_MIN_TMS 1 +#define EMEMORYOTP_MIN_TCS 10 +#define EMEMORYOTP_MIN_TMH 1 +#define EMEMORYOTP_MIN_TAS 50
+#define EMEMORYOTP_MAX_TCD 1 +#define EMEMORYOTP_MIN_TKH 1
+// Note: This has an upper limit of 100. +#define EMEMORYOTP_MIN_TCSP 10 +#define EMEMORYOTP_TYP_TCSP 11
+// This has an upper limit of 20. +#define EMEMORYOTP_MIN_TPPS 5 +#define EMEMORYOTP_TYP_TPPS 6
+// This has an upper limit of 20. +#define EMEMORYOTP_MIN_TPPH 1 +#define EMEMORYOTP_TYP_TPPH 2
+// This has upper limit of 100. +#define EMEMORYOTP_MIN_TPPR 5 +#define EMEMORYOTP_TYP_TPPR 6
+// This has upper limit of 20 +#define EMEMORYOTP_MIN_TPW 10 +#define EMEMORYOTP_TYP_TPW 11
+#define EMEMORYOTP_MIN_TASP 1 +#define EMEMORYOTP_MIN_TDSP 1
+#define EMEMORYOTP_MIN_TAHP 1 +#define EMEMORYOTP_MIN_TDHP 1 +// This has a max of 5! +#define EMEMORYOTP_MIN_TPWI 1 +#define EMEMORYOTP_TYP_TPWI 2
+#endif /* _OTP_FU540_H */ diff --git a/arch/riscv/include/asm/arch-fu540/spi.h b/arch/riscv/include/asm/arch-fu540/spi.h new file mode 100644 index 0000000000..ea3f5344b7 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/spi.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019 SiFive, Inc.
- Authors:
- Pragnesh Patel pragnesh.patel@sifive.com
- Troy Benjegerdes troy.benjegerdes@sifive.com
- */
+#ifndef _SPI_FU540_H +#define _SPI_FU540_H
+/* Register offsets */
+#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18
+#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e
+#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54
+#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64
+#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74
+/* Fields */
+#define SPI_SCK_PHA 0x1 +#define SPI_SCK_POL 0x2
+#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
+/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff)
+#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2
+#define SPI_FCTRL_EN 0x1
+#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) #define +SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
+#define SPI_TXFIFO_FULL BIT(31) +#define SPI_RXFIFO_EMPTY BIT(31)
+/* Values */
+#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3
+#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1
+#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2
+#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1
+#endif /* _SPI_FU540_H */ diff --git a/arch/riscv/include/asm/arch-fu540/uart.h b/arch/riscv/include/asm/arch-fu540/uart.h new file mode 100644 index 0000000000..31ae079a18 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/uart.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019 SiFive, Inc.
- Authors:
- Pragnesh Patel pragnesh.patel@sifive.com
- Troy Benjegerdes troy.benjegerdes@sifive.com
- */
+#ifndef _UART_FU540_H +#define _UART_FU540_H
+/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18
+/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXNSTOP 0x2 +#define UART_TXWM(x) (((x) & 0xffff) << 16)
+/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16)
+/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2
+#endif /* _UART_FU540_H */
One generic comment, I think we need add these header files at the same time when we add something to the FU540 SoC support, and I doubt all of them are needed.
I have added this header files for SPL support, I will recheck if not all of them are needed, thanks for the review.
Regards, Bin