Implement SPI AHB and MOD clocks for all Allwinner SoC clock drivers via clock map descriptor table.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a10.c | 9 +++++++++ drivers/clk/sunxi/clk_a10s.c | 7 +++++++ drivers/clk/sunxi/clk_a31.c | 9 +++++++++ drivers/clk/sunxi/clk_a64.c | 5 +++++ drivers/clk/sunxi/clk_h3.c | 5 +++++ drivers/clk/sunxi/clk_v3s.c | 3 +++ 6 files changed, 38 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 55176bc174..ee499c402a 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -22,12 +22,21 @@ static struct ccu_clk_map a10_clks[] = { [CLK_AHB_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL }, [CLK_AHB_MMC3] = { 0x060, BIT(11), NULL }, + [CLK_AHB_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, + [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, + [CLK_AHB_SPI3] = { 0x060, BIT(23), NULL },
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, [CLK_MMC3] = { 0x094, BIT(31), &mmc_clk_set_rate },
+ [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_SPI2] = { 0x0a8, BIT(31), NULL }, + [CLK_SPI3] = { 0x0d4, BIT(31), NULL }, + [CLK_USB_OHCI0] = { 0x0cc, BIT(6), NULL }, [CLK_USB_OHCI1] = { 0x0cc, BIT(7), NULL }, [CLK_USB_PHY] = { 0x0cc, BIT(8), NULL }, diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index fbac0ad751..bca248f59f 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -19,6 +19,9 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_AHB_MMC0] = { 0x060, BIT(8), NULL }, [CLK_AHB_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_AHB_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, + [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
#ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, @@ -26,6 +29,10 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, #endif
+ [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_SPI2] = { 0x0a8, BIT(31), NULL }, + [CLK_USB_OHCI] = { 0x0cc, BIT(6), NULL }, [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 15076d0e72..1fa77e1272 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -17,6 +17,10 @@ static struct ccu_clk_map a31_clks[] = { [CLK_AHB1_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB1_MMC2] = { 0x060, BIT(10), NULL }, [CLK_AHB1_MMC3] = { 0x060, BIT(12), NULL }, + [CLK_AHB1_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_AHB1_SPI1] = { 0x060, BIT(21), NULL }, + [CLK_AHB1_SPI2] = { 0x060, BIT(22), NULL }, + [CLK_AHB1_SPI3] = { 0x060, BIT(23), NULL }, [CLK_AHB1_OTG] = { 0x060, BIT(24), NULL }, [CLK_AHB1_EHCI0] = { 0x060, BIT(26), NULL }, [CLK_AHB1_EHCI1] = { 0x060, BIT(27), NULL }, @@ -29,6 +33,11 @@ static struct ccu_clk_map a31_clks[] = { [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, [CLK_MMC3] = { 0x094, BIT(31), &mmc_clk_set_rate },
+ [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_SPI2] = { 0x0a8, BIT(31), NULL }, + [CLK_SPI3] = { 0x0ac, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 9ef9b606d2..aa2e69d0a3 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -16,6 +16,8 @@ static struct ccu_clk_map a64_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_BUS_SPI1] = { 0x060, BIT(21), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, [CLK_BUS_EHCI0] = { 0x060, BIT(24), NULL }, [CLK_BUS_EHCI1] = { 0x060, BIT(25), NULL }, @@ -26,6 +28,9 @@ static struct ccu_clk_map a64_clks[] = { [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
+ [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_HSIC] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index ad15aaae67..386289b654 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -16,6 +16,8 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, + [CLK_BUS_SPI1] = { 0x060, BIT(21), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, [CLK_BUS_EHCI0] = { 0x060, BIT(24), NULL }, [CLK_BUS_EHCI1] = { 0x060, BIT(25), NULL }, @@ -30,6 +32,9 @@ static struct ccu_clk_map h3_clks[] = { [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
+ [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_SPI1] = { 0x0a4, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 6eeec201a2..1cca57e065 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -16,12 +16,15 @@ static struct ccu_clk_map v3s_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(24), NULL },
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
+ [CLK_SPI0] = { 0x0a0, BIT(31), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, };