Re: [PATCH] clk: zynqmp: Add set_rate support for display clocks

On 7/11/24 10:29, Venkatesh Yadav Abbarapu wrote:

If "assigned-clock-rates" property is included in the device tree, display driver probe is getting failed, as dp_video_ref till dp_stc_ref clocks are missing from set rate function, adding them to fix the probe failure.

Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com

drivers/clk/clk_zynqmp.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 5999926614..5635451821 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -727,6 +727,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref:

• case dp_video_ref ... dp_stc_ref: return zynqmp_clk_set_peripheral_rate(priv, id, rate, two_divs); default:

Applied. M