Microcode updates are stored in the device tree. Work through these and apply any that are needed.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/cpu.c | 5 + arch/x86/cpu/ivybridge/microcode_intel.c | 150 ++++++++++++++++++++++++ arch/x86/include/asm/arch-ivybridge/microcode.h | 20 ++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 6 files changed, 178 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/microcode_intel.c create mode 100644 arch/x86/include/asm/arch-ivybridge/microcode.h
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index ce16697..a3ea566 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,4 +7,5 @@ obj-y += car.o obj-y += cpu.o obj-y += lpc.o +obj-y += microcode_intel.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index e73ccb7..bd2660f 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -19,6 +19,7 @@ #include <asm/post.h> #include <asm/processor.h> #include <asm/arch/model_206ax.h> +#include <asm/arch/microcode.h> #include <asm/arch/pch.h>
DECLARE_GLOBAL_DATA_PTR; @@ -198,6 +199,10 @@ int print_cpuinfo(void) if (ret) return ret;
+ ret = microcode_update_intel(); + if (ret && ret != -ENOENT && ret != -EEXIST) + return ret; + /* Print processor name */ name = cpu_get_name(processor_name); printf("CPU: %s\n", name); diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/ivybridge/microcode_intel.c new file mode 100644 index 0000000..fbb55f2 --- /dev/null +++ b/arch/x86/cpu/ivybridge/microcode_intel.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2014 Google, Inc + * Copyright (C) 2000 Ronald G. Minnich + * + * Microcode update for Intel PIII and later CPUs + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <asm/msr.h> +#include <asm/processor.h> + +/** + * struct microcode_update - standard microcode header from Intel + * + * We read this information out of the device tree and use it to determine + * whether the update is applicable or not. We also use the same structure + * to read information from the CPU. + */ +struct microcode_update { + uint header_version; + uint update_revision; + uint date_code; + uint processor_signature; + uint checksum; + uint loader_revision; + uint processor_flags; + const void *data; + int size; +}; + +static int microcode_decode_node(const void *blob, int node, + struct microcode_update *update) +{ + update->data = fdt_getprop(blob, node, "data", &update->size); + if (!update->data) + return -EINVAL; + + update->header_version = fdtdec_get_int(blob, node, + "intel,header-version", 0); + update->update_revision = fdtdec_get_int(blob, node, + "intel,update-revision", 0); + update->date_code = fdtdec_get_int(blob, node, + "intel,date-code", 0); + update->processor_signature = fdtdec_get_int(blob, node, + "intel.processor-signature", 0); + update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0); + update->loader_revision = fdtdec_get_int(blob, node, + "loader-revision", 0); + update->processor_flags = fdtdec_get_int(blob, node, + "processor-flags", 0); + + return 0; +} + +static uint32_t microcode_read_rev(void) +{ + /* + * Some Intel CPUs can be very finicky about the CPUID sequence used. + * So this is implemented in assembly so that it works reliably. + */ + uint32_t low, high; + + asm volatile ( + "xorl %%eax, %%eax\n" + "xorl %%edx, %%edx\n" + "movl $0x8b, %%ecx\n" + "wrmsr\n" + "movl $0x01, %%eax\n" + "cpuid\n" + "movl $0x8b, %%ecx\n" + "rdmsr\n" + : /* outputs */ + "=a" (low), "=d" (high) + : /* inputs */ + : /* clobbers */ + "ebx", "ecx" + ); + + return high; +} + +static void microcode_read_cpu(struct microcode_update *cpu) +{ + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ + unsigned int x86_model, x86_family; + struct cpuid_result result; + uint32_t low, high; + + wrmsr(0x8b, 0, 0); + result = cpuid(1); + rdmsr(0x8b, low, cpu->update_revision); + x86_model = (result.eax >> 4) & 0x0f; + x86_family = (result.eax >> 8) & 0x0f; + cpu->processor_signature = result.eax; + + cpu->processor_flags = 0; + if ((x86_model >= 5) || (x86_family > 6)) { + rdmsr(0x17, low, high); + cpu->processor_flags = 1 << ((high >> 18) & 7); + } + debug("microcode: sig=%#x pf=%#x revision=%#x\n", + cpu->processor_signature, cpu->processor_flags, + cpu->update_revision); +} + +/* Get a microcode update from the device tree and apply it */ +int microcode_update_intel(void) +{ + struct microcode_update cpu, update; + const void *blob = gd->fdt_blob; + int count; + int node; + int ret; + + microcode_read_cpu(&cpu); + node = 0; + count = 0; + do { + node = fdtdec_next_compatible(blob, node, + COMPAT_INTEL_MICROCODE); + if (node < 0) { + debug("%s: Found %d updates\n", __func__, count); + return count ? 0 : -ENOENT; + } + + ret = microcode_decode_node(blob, node, &update); + if (ret) { + debug("%s: Unable to decode update: %d\n", __func__, + ret); + return ret; + } + if (update.processor_signature == cpu.processor_signature && + (update.processor_flags & cpu.processor_flags)) { + debug("%s: Update already exists\n", __func__); + return -EEXIST; + } + + wrmsr(0x79, (ulong)update.data, 0); + debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n", + microcode_read_rev(), update.date_code & 0xffff, + (update.date_code >> 24) & 0xff, + (update.date_code >> 16) & 0xff); + count++; + } while (1); +} diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h new file mode 100644 index 0000000..bc9b87c --- /dev/null +++ b/arch/x86/include/asm/arch-ivybridge/microcode.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MICROCODE_H +#define __ASM_ARCH_MICROCODE_H + +/** + * microcode_update_intel() - Apply microcode updates + * + * Applies any microcode updates in the device tree. + * + * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if + * not updates were found, -EINVAL if an update was invalid + */ +int microcode_update_intel(void); + +#endif diff --git a/include/fdtdec.h b/include/fdtdec.h index 6b40006..3bd60b7 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -118,6 +118,7 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ + COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4aa227a..9a68f9c 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(PARADE_PS8625, "parade,ps8625"), COMPAT(COMPAT_INTEL_LPC, "intel,lpc"), + COMPAT(INTEL_MICROCODE, "intel,microcode"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)