Dear Fabio Estevam,
On Fri, Apr 26, 2013 at 3:16 PM, Marek Vasut marex@denx.de wrote:
http://s8.postimg.org/dn7jhntut/imx233_olinuxino_maxi_2_5_V_rising.jpg check this, this is as much as I got from tsvetan so far, it's the VDDMEM ramping. I dunno what's that weird drop before it starts going from 1V5 to 2V5, but it's strange at best and I don't like it. I think that's also the source of our problems, the DRAM suffers undervolt and quickly afterwards is configured for regular operation ... I'd say check mx23_mem_setup_vddmem() and inspect the
Currently mx23_mem_setup_vddmem() does not clear ENABLE_ILIMIT bit as recommended by the mx23 Reference Manual:
"Controls the inrush limit (~10mA) for the memory supply voltage. Default is active. This should remain active until the supply settles after enabling the linreg. This should be disabled before accessing the memory."
FSL bootlets does clear this bit.
I did the same as FSL bootlets locally and this alone does not allowed me to boot the kernel without bumping VDDMEM to 2.6V.
I can send a patch that clears ENABLE_LIMIT, after this one gets applied.
Fabio, can you get someone in FSL to measure all these VDDx (VDDD, VDDA, VDDIO, VDDMEM) rails with stock 2013.04 U-Boot image from powerup to u-boot command line and send us the results? You'd need a scope that can produce an image of what's happening on the rails. I just can't figure out how to get this displayed on my scope, sorry :-(
Best regards, Marek Vasut