Hi Bin,
On 10 July 2015 at 09:39, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Fri, Jul 10, 2015 at 8:55 PM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 6 July 2015 at 02:31, Bin Meng bmeng.cn@gmail.com wrote:
We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f().
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Changes in v2: None
arch/x86/cpu/cpu.c | 22 ++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++----------- 2 files changed, 38 insertions(+), 11 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index d108ee5..9afdafb 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -28,6 +28,8 @@ #include <asm/cpu.h> #include <asm/lapic.h> #include <asm/mp.h> +#include <asm/msr.h> +#include <asm/mtrr.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/processor-flags.h> @@ -352,6 +354,26 @@ int x86_cpu_init_f(void) gd->arch.has_mtrr = has_mtrr(); }
/* Configure fixed range MTRRs for some legacy regions */if (gd->arch.has_mtrr) {u64 mtrr_cap;mtrr_cap = native_read_msr(MTRR_CAP_MSR);if (mtrr_cap & MTRR_CAP_FIX) {/* Mark the VGA RAM area as uncacheable */native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);/* Mark the PCI ROM area as uncacheable */native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);I just noticed that setting this up makes the Minnowmax ROM execution go really slowly. Do we need to turn off the cache? It goes from <1s to >4s.
Oops, that's bad. I guess we should turn on the cache for the rom execution then. BTW I found the tunnelcreek vbios changed the Cseg MTRR to write-through itself.
OK - can you try to do a patch for that? But first, why do we need to make the area uncacheable?
Regards, Simon