Re: [U-Boot] [PATCH 29/35] arm: socfpga: cache: Define cacheline size

15 Sep 2014


      On Mon 2014-09-15 13:06:22, Marek Vasut wrote:
...
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut marex@denx.de
Cc: Chin Liang See clsee@altera.com
Cc: Dinh Nguyen dinguyen@altera.com
Cc: Albert Aribaud albert.u.boot@aribaud.net
Cc: Tom Rini trini@ti.com
Cc: Wolfgang Denk wd@denx.de
Acked-by: Pavel Machek pavel@denx.de
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