On Mon, Aug 22, 2016 at 10:34:15AM -0600, Stephen Warren wrote:
On 08/22/2016 06:22 AM, Tom Rini wrote:
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment.
Tested-by: Stephen Warren swarren@nvidia.com
Thanks.
This has the potential to cause a few more cache warnings due to the slightly stricter/larger alignment checking on older ARMv7s with smaller cache lines. However, it works fine on all the Tegra systems my automated tests run on right now, which does include one Cortex A9 with 32-byte cache line, and doesn't seem to actually trigger any additional unaligned buffer warnings.
I didn't spell it out, but this patch is a pre-req for Stefan's series that should fix most/all of the cache warning. I can't bring that in as there's cases where we didn't define the cache size today and rather than add a default 32 in one more place I figured it was time to tackle it this way.