From: Gowtham Tammana g-tammana@ti.com
Main domain ESM support is needed to configure main domain watchdog interrupts to generate ESM pin events. On J7200 boards ESM error pin output is propagated to PMIC to generate reset.
Signed-off-by: Gowtham Tammana g-tammana@ti.com Signed-off-by: Neha Malcom Francis n-francis@ti.com --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 4 ++++ arch/arm/dts/k3-j7200-main.dtsi | 6 ++++++ arch/arm/dts/k3-j7200.dtsi | 1 + 3 files changed, 11 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index f57c2306ba..088fdb4072 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -196,3 +196,7 @@ &main_r5fss0 { ti,cluster-mode = <0>; }; + +&main_esm { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index e8a41d09b4..4c8ba123dc 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -774,4 +774,10 @@ ti,loczrama = <1>; }; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <656>, <657>; + }; }; diff --git a/arch/arm/dts/k3-j7200.dtsi b/arch/arm/dts/k3-j7200.dtsi index b7005b8031..9252d97399 100644 --- a/arch/arm/dts/k3-j7200.dtsi +++ b/arch/arm/dts/k3-j7200.dtsi @@ -124,6 +124,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */