On 26.06.2018 23:24, Han Xu wrote:
On 04/20/2018 10:53 AM, Stefan Agner wrote:
From: Stefan Agner stefan.agner@toradex.com
Signed-off-by: Stefan Agner stefan.agner@toradex.com
arch/arm/dts/imx7-colibri.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts index f6c21052ae..a3b5618b45 100644 --- a/arch/arm/dts/imx7-colibri.dts +++ b/arch/arm/dts/imx7-colibri.dts @@ -17,6 +17,15 @@ }; };
+&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- fsl,use-minimum-ecc;
enable minimum ecc may cause no backward compatible since previous implementation use oob space for ecc as much as possible. May consider mention this in docs and don't enable it by default?
Yes I am aware of that.
Unfortunately, we ship already lots of products with downstream kernels. And those kernels seem to default to a behavior which is similar to mainlines "fsl,use-minimum-ecc". So with this change I only make sure that upstream kernels work with the layout used in downstream U-Boot/Linux.
-- Stefan
- nand-on-flash-bbt;
- nand-ecc-mode = "hw";
- status = "okay";
+};
- &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>;
@@ -49,6 +58,25 @@ };
&iomuxc {
- pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <MX7D_PAD_SD3_CLK__NAND_CLE 0x71MX7D_PAD_SD3_CMD__NAND_ALE 0x71MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71>;- };
- pinctrl_i2c4: i2c4-grp { fsl,pins = < MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f