From: Vladimir Oltean vladimir.oltean@nxp.com
Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal.
These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c
Signed-off-by: Vladimir Oltean vladimir.oltean@nxp.com --- doc/device-tree-bindings/spi/spi-mcf-dspi.txt | 4 ++ drivers/spi/fsl_dspi.c | 54 ++++++++++++++++++- include/fsl_dspi.h | 1 + 3 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt index 860eb8ac8526..4684d7846a99 100644 --- a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt +++ b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt @@ -13,6 +13,10 @@ Optional properties: - ctar-params: CTAR0 to 7 register configuration, as an array of 8 integer fields for each register, where each register is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>. +- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip + select and the start of clock signal, at the start of a transfer. +- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock + signal and deactivating chip select, at the end of a transfer.
Example:
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index a68a51945e4e..c0303dc5d606 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -9,6 +9,7 @@ * Haikun Wang (B53464@freescale.com) */
+#include <linux/math64.h> #include <common.h> #include <dm.h> #include <errno.h> @@ -22,6 +23,9 @@ #endif #include <fsl_dspi.h>
+/* linux/include/time.h */ +#define NSEC_PER_SEC 1000000000L + DECLARE_GLOBAL_DATA_PTR;
/* fsl_dspi_platdata flags */ @@ -383,6 +387,40 @@ static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br, return -EINVAL; }
+static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns, + unsigned long clkrate) +{ + int scale_needed, scale, minscale = INT_MAX; + int pscale_tbl[4] = {1, 3, 5, 7}; + u32 remainder; + int i, j; + + scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, + &remainder); + if (remainder) + scale_needed++; + + for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) + for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) { + scale = pscale_tbl[i] * (2 << j); + if (scale >= scale_needed) { + if (scale < minscale) { + minscale = scale; + *psc = i; + *sc = j; + } + break; + } + } + + if (minscale == INT_MAX) { + pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", + delay_ns, clkrate); + *psc = ARRAY_SIZE(pscale_tbl) - 1; + *sc = DSPI_CTAR_SCALE_BITS; + } +} + static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed) { int ret; @@ -540,6 +578,9 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev) { struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); struct fsl_dspi_priv *priv = dev_get_priv(dev->parent); + u32 cs_sck_delay = 0, sck_cs_delay = 0; + unsigned char pcssck = 0, cssck = 0; + unsigned char pasc = 0, asc = 0;
if (slave_plat->cs >= priv->num_chipselect) { debug("DSPI invalid chipselect number %d(max %d)!\n", @@ -547,7 +588,18 @@ static int fsl_dspi_child_pre_probe(struct udevice *dev) return -EINVAL; }
- priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE; + ofnode_read_u32(dev->node, "fsl,spi-cs-sck-delay", &cs_sck_delay); + ofnode_read_u32(dev->node, "fsl,spi-sck-cs-delay", &sck_cs_delay); + + /* Set PCS to SCK delay scale values */ + ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk); + + /* Set After SCK delay scale values */ + ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk); + + priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE | + DSPI_CTAR_PCSSCK(pcssck) | + DSPI_CTAR_PASC(pasc);
debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n", slave_plat->cs, slave_plat->max_hz, slave_plat->mode); diff --git a/include/fsl_dspi.h b/include/fsl_dspi.h index 114f63bce374..4fec83549e1f 100644 --- a/include/fsl_dspi.h +++ b/include/fsl_dspi.h @@ -94,6 +94,7 @@ struct dspi { #define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8) #define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4) #define DSPI_CTAR_BR(x) ((x) & 0x0F) +#define DSPI_CTAR_SCALE_BITS 0xf
/* Status */ #define DSPI_SR_TCF 0x80000000