This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs using the new infrastructure.
Existing nand_spl targets are updated to deal with the name change from nand_init.c to spl_minimal.c (as in theory this isn't limited to NAND anymore).
Signed-off-by: Scott Wood scottwood@freescale.com Cc: Kim Phillips kim.phillips@freescale.com --- README | 6 +++ arch/powerpc/cpu/mpc83xx/Makefile | 16 ++++++ .../cpu/mpc83xx/{nand_init.c => spl_minimal.c} | 0 arch/powerpc/cpu/mpc83xx/start.S | 31 ++++++----- arch/powerpc/cpu/mpc83xx/u-boot-spl.lds | 55 ++++++++++++++++++++ arch/powerpc/lib/Makefile | 3 +- nand_spl/board/freescale/mpc8313erdb/Makefile | 6 +-- nand_spl/board/freescale/mpc8315erdb/Makefile | 6 +-- nand_spl/board/sheldon/simpc8313/Makefile | 6 +-- 9 files changed, 107 insertions(+), 22 deletions(-) rename arch/powerpc/cpu/mpc83xx/{nand_init.c => spl_minimal.c} (100%) create mode 100644 arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
diff --git a/README b/README index 3c3de4f..57a42ed 100644 --- a/README +++ b/README @@ -2727,6 +2727,12 @@ FIT uImage format: CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME Filename to read to load U-Boot when reading from FAT
+ CONFIG_SPL_MPC83XX_WAIT_FOR_NAND + Set this for NAND SPL on PPC mpc83xx targets, so that + start.S waits for the rest of the SPL to load before + continuing (the hardware starts execution after just + loading the first page rather than the full 4K). + CONFIG_SPL_NAND_BASE Include nand_base.c in the SPL. Requires CONFIG_SPL_NAND_DRIVERS. diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 687f5e9..8a470b8 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -27,8 +27,22 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).o
+MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + START = start.o
+ifdef MINIMAL + +COBJS-y += spl_minimal.o + +else + COBJS-y += traps.o COBJS-y += cpu.o COBJS-y += cpu_init.o @@ -51,6 +65,8 @@ COBJS-y += spd_sdram.o endif COBJS-$(CONFIG_FSL_DDR2) += law.o
+endif # not minimal + COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y)) diff --git a/arch/powerpc/cpu/mpc83xx/nand_init.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c similarity index 100% rename from arch/powerpc/cpu/mpc83xx/nand_init.c rename to arch/powerpc/cpu/mpc83xx/spl_minimal.c diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b70b4ca..44a64b7 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -58,7 +58,13 @@ #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) #endif
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_NAND_SPL) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) +#define MINIMAL_SPL +#endif + +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ + !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_FLASHBOOT #endif
@@ -72,7 +78,7 @@ GOT_ENTRY(__bss_start) GOT_ENTRY(__bss_end__)
-#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL GOT_ENTRY(_FIXUP_TABLE_) GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) @@ -206,7 +212,8 @@ _start: /* time t 0 */ /* Initialise the E300 processor core */ /*------------------------------------------*/
-#ifdef CONFIG_NAND_SPL +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ + defined(CONFIG_NAND_SPL) /* The FCM begins execution after only the first page * is loaded. Wait for the rest before branching * to another flash page. @@ -292,7 +299,7 @@ in_flash:
/* NOTREACHED - board_init_f() does not return */
-#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Vector Table */ @@ -467,7 +474,7 @@ int_return: lwz r1,GPR1(r1) SYNC rfi -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */
/* * This code initialises the E300 processor core @@ -724,7 +731,7 @@ setup_bats: * Note: requires that all cache bits in * HID0 are in the low half word. */ -#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL .globl icache_enable icache_enable: mfspr r3, HID0 @@ -753,7 +760,7 @@ icache_status: mfspr r3, HID0 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */
.globl dcache_enable dcache_enable: @@ -936,7 +943,7 @@ in_ram: stw r0,0(r3) 2: bdnz 1b
-#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. @@ -991,7 +998,7 @@ clear_bss: mr r4, r10 /* Destination Address */ bl board_init_r
-#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL /* * Copy exception vector code to low memory * @@ -1061,7 +1068,7 @@ trap_init: mtlr r4 /* restore link register */ blr
-#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */
#ifdef CONFIG_SYS_INIT_RAM_LOCK lock_ram_in_cache: @@ -1085,7 +1092,7 @@ lock_ram_in_cache: sync blr
-#ifndef CONFIG_NAND_SPL +#ifndef MINIMAL_SPL .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1111,7 +1118,7 @@ unlock_ram_in_cache: sync mtspr HID0, r3 /* no invalidate, unlock */ blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !MINIMAL_SPL */ #endif /* CONFIG_SYS_INIT_RAM_LOCK */
#ifdef CONFIG_SYS_FLASHBOOT diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds new file mode 100644 index 0000000..d140453 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + . = ALIGN(16); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { + *(.*bss) + } + __bss_end__ = .; +} +ENTRY(_start) +ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big"); diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 844fe86..86cf02a 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -47,7 +47,8 @@ endif endif
ifdef MINIMAL -COBJS-y += cache.o +COBJS-y += cache.o time.o +SOBJS-y += ticks.o else
SOBJS-y += ppcstring.o diff --git a/nand_spl/board/freescale/mpc8313erdb/Makefile b/nand_spl/board/freescale/mpc8313erdb/Makefile index cff2a43..f997b5f 100644 --- a/nand_spl/board/freescale/mpc8313erdb/Makefile +++ b/nand_spl/board/freescale/mpc8313erdb/Makefile @@ -36,7 +36,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -80,8 +80,8 @@ $(obj)$(BOARD).c: $(obj)ns16550.c: ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-$(obj)nand_init.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c +$(obj)spl_minimal.c: + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c
$(obj)cache.c: ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile index cff2a43..f997b5f 100644 --- a/nand_spl/board/freescale/mpc8315erdb/Makefile +++ b/nand_spl/board/freescale/mpc8315erdb/Makefile @@ -36,7 +36,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -80,8 +80,8 @@ $(obj)$(BOARD).c: $(obj)ns16550.c: ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-$(obj)nand_init.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c +$(obj)spl_minimal.c: + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c
$(obj)cache.c: ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile index 2a3ddac..d967846 100644 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -36,7 +36,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -84,9 +84,9 @@ $(obj)ns16550.c: @rm -f $@ ln -s $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)nand_init.c: +$(obj)spl_minimal.c: @rm -f $@ - ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
$(obj)cache.c: @rm -f $@