Re: [U-Boot] [PATCH 2/7] ARM: BeagleBoard-X15: Enable HW leveling

Hi,

On Monday 14 December 2015 06:40 PM, Dmitry Lifshitz wrote:

Hi Lokesh,

We are working on U-Boot for CompuLab board based on AM57xx SoC (CL-SOM-AM57x).

We figured out the following note in AM57xx TRM for EMIF register EMIF_DDR_PHY_CONTROL_1, bits 25:27 (WRLVL_MASK, RDLVLGATE_MASK, RDLVL_MASK)

"NOTE: Read-Write Leveling is not supported on this device. Set this value to 0x1."

Actually this is not true. It is supported and has been successfully tested. TRM needs to be updated. Thanks for catching this. Ill take the necessary steps for this update in TRM.

Thanks and regards, Lokesh

This contradicts with the following patch, enabling HW leveling for BeagleBoard-X15.

Please, advice, if it save and required to apply HW leveling related registers settings.

Does DRA7x DDR3 HW leveling code is relevant for AM57xx ?

Thank you,

Dmitry Lifshitz

On 06/03/2015 12:13 PM, Lokesh Vutla wrote:

...

Updating EMIF registers to enable HW leveling on BeagleBoard-X15.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com

board/ti/beagle_x15/board.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 75dd8e8..76654c8 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -55,15 +55,15 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,

• .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
• .emif_ddr_phy_ctlr_1 = 0x0e24400a,

• .emif_ddr_phy_ctlr_1_init = 0x0024400b,
• .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000,

• .emif_rd_wr_lvl_rmp_ctl = 0x00000000,

• .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };

@@ -103,7 +103,12 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,

• 0x00400040

• 0x00400040,

• 0x0,

• 0x0,

• 0x0,

• 0x0,

• 0x0 };

  static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs

= { @@ -118,15 +123,15 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .read_idle_ctrl = 0x00050001, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000,

• .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
• .emif_ddr_phy_ctlr_1 = 0x0e24400a,

• .emif_ddr_phy_ctlr_1_init = 0x0024400b,
• .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000,

• .emif_rd_wr_lvl_rmp_ctl = 0x00000000,

• .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 };

@@ -163,7 +168,12 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00400040, 0x00400040, 0x00400040,

• 0x00400040

• 0x00400040,

• 0x0,

• 0x0,

• 0x0,

• 0x0,

• 0x0 };

  void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)