Improve PLL freq computation by using the full resolution of the PLL registers
Signed-off-by: Eric Jarrige eric.jarrige@armadeus.org Cc: Stefano Babic sbabic@denx.de --- arch/arm/cpu/arm920t/imx/speed.c | 29 +++++++++++------------------ 1 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c index 1e29698..b1c2bd6 100644 --- a/arch/arm/cpu/arm920t/imx/speed.c +++ b/arch/arm/cpu/arm920t/imx/speed.c @@ -36,33 +36,26 @@ * the specified bus in HZ. */ /* ------------------------------------------------------------------------- */ - -ulong get_systemPLLCLK(void) +static ulong get_PLLCLK(u32 sys_clk_freq, u32 pllctl0) { /* FIXME: We assume System_SEL = 0 here */ - u32 spctl0 = SPCTL0; - u32 mfi = (spctl0 >> 10) & 0xf; - u32 mfn = spctl0 & 0x3f; - u32 mfd = (spctl0 >> 16) & 0x3f; - u32 pd = (spctl0 >> 26) & 0xf; + u32 mfi = (pllctl0 >> 10) & 0xf; + u32 mfn = pllctl0 & 0x3ff; + u32 mfd = (pllctl0 >> 16) & 0x3ff; + u32 pd = (pllctl0 >> 26) & 0xf;
mfi = mfi<=5 ? 5 : mfi; + return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1)); +}
- return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); +ulong get_systemPLLCLK(void) +{ + return get_PLLCLK(CONFIG_SYSPLL_CLK_FREQ, SPCTL0); }
ulong get_mcuPLLCLK(void) { - /* FIXME: We assume System_SEL = 0 here */ - u32 mpctl0 = MPCTL0; - u32 mfi = (mpctl0 >> 10) & 0xf; - u32 mfn = mpctl0 & 0x3f; - u32 mfd = (mpctl0 >> 16) & 0x3f; - u32 pd = (mpctl0 >> 26) & 0xf; - - mfi = mfi<=5 ? 5 : mfi; - - return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); + return get_PLLCLK(CONFIG_SYS_CLK_FREQ, MPCTL0); }
ulong get_FCLK(void)