-----Original Message----- From: Michael Walle [mailto:michael@walle.cc] Sent: 01 February 2012 04:53 To: u-boot@lists.denx.de Cc: Michael Walle; Albert ARIBAUD; Prafulla Wadaskar; Wolfgang Denk Subject: [PATCH v3] arm, arm-kirkwood: disable l2c before linux boot
The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
Signed-off-by: Michael Walle michael@walle.cc Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Prafulla Wadaskar prafulla@marvell.com Cc: Wolfgang Denk wd@denx.de
v3: remove unused enable function
v2: replace magic number with macro
arch/arm/cpu/arm926ejs/cache.c | 9 ++++++++ arch/arm/cpu/arm926ejs/cpu.c | 2 + arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 + arch/arm/cpu/arm926ejs/kirkwood/cache.c | 34 ++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index ee90ab7..504f604 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -68,3 +68,12 @@ void flush_cache(unsigned long start, unsigned long size) { } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+/*
- Stub implementations for l2 cache operations
- */
+void __l2_cache_disable(void) +{ +} +void l2_cache_disable(void)
__attribute__((weak, alias("__l2_cache_disable")));diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 5c902df..626384c 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -50,6 +50,8 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ icache_disable(); dcache_disable();
- l2_cache_disable();
- /* flush I/D-cache */ cache_flush();
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 0754297..777006c 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile @@ -30,6 +30,7 @@ COBJS-y = cpu.o COBJS-y += dram.o COBJS-y += mpp.o COBJS-y += timer.o +COBJS-y += cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c new file mode 100644 index 0000000..3e73565 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c @@ -0,0 +1,34 @@ +/*
- Copyright (c) 2011 Michael Walle
Please change this to 2012, otherwise ack for rest of the patch.
Regards.. Prafulla . . .