Re: [U-Boot] clk: clk_stm32f7: fix PLL clock division factor

On Thu, Oct 26, 2017 at 01:23:19PM +0200, patrice.chotard@st.com wrote:

From: Patrice Chotard patrice.chotard@st.com

Fix clock division factor initialization for RCC_PLLCFGR registers.

PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared, it's a forbidden value. So update RCC_PLLCFGR using clrsetbits_le32() to set only necessary bits fields.

Signed-off-by: Patrice Chotard patrice.chotard@st.com Reviewed-by: Simon Glass sjg@chromium.org

Applied to u-boot/master, thanks!