This init can be done in the northbridge's probe() method. Move it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/ivybridge/northbridge.c | 17 +++++++++++++++++ arch/x86/cpu/ivybridge/pci.c | 20 -------------------- 2 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index e03e472..ee09103 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -14,6 +14,7 @@ #include <asm/cpu.h> #include <asm/io.h> #include <asm/pci.h> +#include <asm/post.h> #include <asm/processor.h> #include <asm/arch/pch.h> #include <asm/arch/model_206ax.h> @@ -283,9 +284,25 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev)
static int bd82x6x_northbridge_probe(struct udevice *dev) { + u16 reg16; + if (!(gd->flags & GD_FLG_RELOC)) return bd82x6x_northbridge_early_init(dev);
+ reg16 = 0xff; + dm_pci_read_config16(dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + dm_pci_write_config16(dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + dm_pci_write_config16(dev, PCI_STATUS, 0xffff); + dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); + dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x08); + dm_pci_write_bar32(dev, 0, 0xf0000000); + post_code(0x52); + bd82x6x_pci_init(dev); northbridge_enable(dev); northbridge_init(dev); diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index 8af99b4..b081469 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -19,32 +19,12 @@
static int pci_ivybridge_probe(struct udevice *bus) { - struct pci_controller *hose = dev_get_uclass_priv(bus); - pci_dev_t dev; - u16 reg16; - if (!(gd->flags & GD_FLG_RELOC)) return 0; post_code(0x50); bd82x6x_init_extra(); post_code(0x51);
- reg16 = 0xff; - dev = PCH_DEV; - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - pci_write_bar32(hose, dev, 0, 0xf0000000); - post_code(0x52); - return 0; }