In preparation for the ARMv8-R64 FVP support, which has DRAM mapped at 0x0, generalise the page table generation, by using symbolic names for the address ranges instead of fixed numbers.
We already define the base of the DRAM and MMIO regions, so just use those symbols in the page table description. Rename V2M_BASE to the more speaking V2M_DRAM_BASE on the way.
On the VExpress memory map, the address space right after 4GB is of no particular interest to software, as the whole of DRAM is mapped at 32GB instead. The first 2 GB alias to the lower 2GB of DRAM mapped below 4GB, so we skip this part and map some more of the high DRAM, should anyone need it.
Signed-off-by: Andre Przywara andre.przywara@arm.com --- board/armltd/vexpress64/vexpress64.c | 24 ++++++++++++++++++------ include/configs/vexpress_aemv8.h | 4 ++-- 2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7d5e5516f9..c3ad1fcc78 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -15,6 +15,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <linux/compiler.h> +#include <linux/sizes.h> #include <dm/platform_data/serial_pl01x.h> #include "pcie.h" #include <asm/armv8/mmu.h> @@ -38,16 +39,27 @@ U_BOOT_DRVINFO(vexpress_serials) = {
static struct mm_region vexpress64_mem_map[] = { { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, + .virt = V2M_PA_BASE, + .phys = V2M_PA_BASE, + .size = SZ_2G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0xff80000000UL, + .virt = V2M_DRAM_BASE, + .phys = V2M_DRAM_BASE, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* + * DRAM beyond 2 GiB is located high. Let's map just some + * of it, although U-Boot won't realistically use it, and + * the actual available amount might be smaller on the model. + */ + .virt = 0x880000000UL, /* 32 + 2 GiB */ + .phys = 0x880000000UL, + .size = 6UL * SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 2bf0c78a56..105f58ac8e 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -20,7 +20,7 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/* CS register bases for the original memory map. */ -#define V2M_BASE 0x80000000 +#define V2M_DRAM_BASE 0x80000000 #define V2M_PA_BASE 0x00000000
#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) @@ -103,7 +103,7 @@ #define CONFIG_BOOTP_BOOTFILESIZE
/* Physical Memory Map */ -#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */ /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE