When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is set in the last BD, which causes FEC transmission to fail.
As explained by Ye Li:
"The TDAR bit is set when the descriptors are all out from TX ring, but the descriptor properly is in transmitting not READY. These are two signals, and in Ic simulation, we found the TDAR always clear prior than the READY bit of last BD. In mx6solox, we use a latest version of FEC IP. It looks the intrinsic behave of TDAR bit is changed in this FEC version, not any bug in mx6sx."
Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm for the other SoCs.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- Changes since v3: - Place invalidate_dcache_range in the correct location Changes since v2: - Poll FEC_TBD_READY after polling TDAR
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- drivers/net/fec_mxc.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cefda4..675d53c 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -711,13 +711,22 @@ static int fec_send(struct eth_device *dev, void *packet, int length) break; }
- if (!timeout) + if (!timeout) { ret = -EINVAL; + goto out; + }
- invalidate_dcache_range(addr, addr + size); - if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) + timeout = FEC_XFER_TIMEOUT; + while (--timeout) { + invalidate_dcache_range(addr, addr + size); + if (!(readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)) + break; + } + + if (!timeout) ret = -EINVAL;
+out: debug("fec_send: status 0x%x index %d ret %i\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index, ret);