Re: [PATCH] k3: pmic: Clear ESM masks

On Wed, Apr 05, 2023 at 04:24:35PM +0530, Neha Malcom Francis wrote:

ESM MCU masks must be set to 0h so that PMIC can handle errors that require attention for example SYS_SAFETY_ERRn. The required bits must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK.

If PMIC expected to handle errors, make sure EVM is configured to connect SOC_SAFETY_ERRz (Main) to the PMIC.

Note that even though the User Guide for TPS65941 for J721E mentions that these bits are reset to 0h; it is not reflected once board boots to kernel, possibly due to NVM configurations. Eithercase, it is best to account for this from R5 SPL side as well.

Signed-off-by: Neha Malcom Francis n-francis@ti.com

Applied to u-boot/master, thanks!