This prevents the scenario where data cache is on and the device uses DMA to deploy data. In that case, it might not be possible to flush/invalidate data to RAM properly. The other option is to use bounce buffer, but that involves a lot of copying and therefore degrades performance rapidly. Therefore disallow this possibility of unaligned load address altogether if data cache is on.
Signed-off-by: Marek Vasut marex@denx.de Cc: Joe Hershberger joe.hershberger@gmail.com --- common/cmd_net.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/common/cmd_net.c b/common/cmd_net.c index a9ade8b..917061b 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -242,6 +242,10 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc, bootstage_error(BOOTSTAGE_ID_NET_START); return CMD_RET_USAGE; } + + if (!cacheline_aligned(load_addr)) + return 1; + bootstage_mark(BOOTSTAGE_ID_NET_START);
if ((size = NetLoop(proto)) < 0) {