From: T Karthik Reddy t.karthik.reddy@xilinx.com
soc_xilinx_zynqmp driver allows identification of family & revision of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP. Add this config to xilinx_zynqmp_virt_defconfig file. Probe this driver using platdata U_BOOT_DEVICE structure which is specified in mach-zynqmp/cpu.c.
Signed-off-by: T Karthik Reddy t.karthik.reddy@xilinx.com Reviewed-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
MAINTAINERS | 1 + arch/arm/Kconfig | 1 + arch/arm/mach-zynqmp/cpu.c | 5 ++ arch/arm/mach-zynqmp/include/mach/hardware.h | 3 + configs/xilinx_zynqmp_virt_defconfig | 1 + drivers/soc/Kconfig | 8 ++ drivers/soc/Makefile | 1 + drivers/soc/soc_xilinx_zynqmp.c | 78 ++++++++++++++++++++ 8 files changed, 98 insertions(+) create mode 100644 drivers/soc/soc_xilinx_zynqmp.c
diff --git a/MAINTAINERS b/MAINTAINERS index 868d4e145ca2..af5a1fedf1d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -602,6 +602,7 @@ F: drivers/net/zynq_gem.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c +F: drivers/soc/soc_xilinx_zynqmp.c F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c F: drivers/timer/cadence-ttc.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3a745ce126aa..3e8a31f8ad56 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1133,6 +1133,7 @@ config ARCH_ZYNQMP select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL select ZYNQMP_IPI + select SOC_DEVICE imply BOARD_LATE_INIT imply CMD_DM imply ENV_VARS_UBOOT_RUNTIME_CONFIG diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 29743cae5aab..26e285c24fe0 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -15,6 +15,7 @@ #include <asm/io.h> #include <zynqmp_firmware.h> #include <asm/cache.h> +#include <dm/platdata.h>
#define ZYNQ_SILICON_VER_MASK 0xF000 #define ZYNQ_SILICON_VER_SHIFT 12 @@ -218,3 +219,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value)
return ret; } + +U_BOOT_DRVINFO(soc_xilinx_zynqmp) = { + .name = "soc_xilinx_zynqmp", +}; diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 37764990707c..eebf38551c2f 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -69,6 +69,9 @@ struct iou_scntr_secure {
#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
+#define ZYNQMP_PS_VERSION 0xFFCA0044 +#define ZYNQMP_PS_VER_MASK GENMASK(1, 0) + /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F #define QSPI_MODE_24BIT 0x00000001 diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 2c888130fa59..5b2f2f69e461 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -160,6 +160,7 @@ CONFIG_DM_SCSI=y CONFIG_ARM_DCC=y CONFIG_XILINX_UARTLITE=y CONFIG_ZYNQ_SERIAL=y +CONFIG_SOC_XILINX_ZYNQMP=y CONFIG_SPI=y CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 864d00a88538..17fb4c4d65e5 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -16,6 +16,14 @@ config SOC_DEVICE_TI_K3 This allows Texas Instruments Keystone 3 SoCs to identify specifics about the SoC in use.
+config SOC_XILINX_ZYNQMP + bool "Enable SoC Device ID driver for Xilinx ZynqMP" + depends on SOC_DEVICE && ARCH_ZYNQMP + help + Enable this option to select SoC device id driver for Xilinx ZynqMP. + This allows other drivers to verify the SoC familiy & revision + using matching SoC attributes. + source "drivers/soc/ti/Kconfig"
endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 9ef20ca5066f..9b26573c71c8 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o obj-$(CONFIG_SANDBOX) += soc_sandbox.o +obj-$(CONFIG_SOC_XILINX_ZYNQMP) += soc_xilinx_zynqmp.o diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c new file mode 100644 index 000000000000..7d33ce2163d8 --- /dev/null +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx ZynqMP SOC driver + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include <common.h> +#include <dm.h> +#include <asm/cache.h> +#include <soc.h> +#include <zynqmp_firmware.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> + +/* + * Zynqmp has 4 silicon revisions + * v0 -> 0(XCZU9EG-ES1) + * v1 -> 1(XCZU3EG-ES1, XCZU15EG-ES1) + * v2 -> 2(XCZU7EV-ES1, XCZU9EG-ES2, XCZU19EG-ES1) + * v3 -> 3(Production Level) + */ +static const char zynqmp_family[] = "ZynqMP"; + +struct soc_xilinx_zynqmp_priv { + const char *family; + char revision; +}; + +static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_xilinx_zynqmp_ops = { + .get_family = soc_xilinx_zynqmp_get_family, + .get_revision = soc_xilinx_zynqmp_get_revision, +}; + +static int soc_xilinx_zynqmp_probe(struct udevice *dev) +{ + struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev); + u32 ret_payload[4]; + int ret; + + priv->family = zynqmp_family; + + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3 || + !IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) + ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]); + else + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret < 0) + return ret; + + priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK; + + return 0; +} + +U_BOOT_DRIVER(soc_xilinx_zynqmp) = { + .name = "soc_xilinx_zynqmp", + .id = UCLASS_SOC, + .ops = &soc_xilinx_zynqmp_ops, + .probe = soc_xilinx_zynqmp_probe, + .priv_auto = sizeof(struct soc_xilinx_zynqmp_priv), + .flags = DM_FLAG_PRE_RELOC, +};