Hello Dirk,
On Mon, May 10, 2010 at 10:02 AM, Dirk Behme dirk.behme@googlemail.com wrote:
Hi George,
On 05.05.2010 23:09, George G. Davis wrote:
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches
... Also flushes the branch target cache"
" when in fact the intent is to "Clean and Invalidate Entire Data Cache".
Why don't we have to invalidate/flush the I- and BT-Cache here? I.e. why is it sufficient to clean & invalidate the D-Cache here, only, and remove the existing I- and BT-Cache invalidation/flushing?
Quite frankly I thought for sure that it was handled elsewhere but now that I look I see that it's not. Meanwhile, I don't think U-Boot is typically susceptible to self-modifying-code issues anyway (?) and this isn't likely required but I suppose lack of I+BTB invalidation could be an issue in some cases, e.g. loading and running a new version of U-Boot from RAM? So better to be safe and restore the I+BTB invalidation here.
What's about just adding an additional clean of the data cache before the 'invalidate all':
- asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
?
That works for me.
If there is no more feedback, I'll resubmit an updated patch.
Thansk!
-- Regards, George
Thanks for finding this and best regards
Dirk