To enable the clocks on the at91 boards a constant (0x4) is used. This is replaced with a define in at91_pmc.h (1 << 2).
Signed-off-by: Erik van Luijk evanluijk@interact.nl --- arch/arm/mach-at91/include/mach/at91_pmc.h | 1 + board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 2 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 2 +- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 2 +- board/atmel/sama5d3xek/sama5d3xek.c | 2 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 +- board/atmel/sama5d4ek/sama5d4ek.c | 2 +- board/siemens/corvus/board.c | 2 +- 9 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index ebb7dec..8a3fb94 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -158,6 +158,7 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91_PMC_DDR (1 << 2) /* DDR Clock */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index d2ade4d..2fea56f 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -136,7 +136,7 @@ void mem_init(void) ddr2_conf(&ddr2);
/* enable DDR2 clock */ - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 8437f37..59bc535 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -316,7 +316,7 @@ void mem_init(void) ddr2_conf(&ddr2);
/* enable DDR2 clock */ - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* Chip select 1 is for DDR2/SDRAM */ csa = readl(&matrix->ebicsa); diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 0455e2c..1738a2b 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -353,7 +353,7 @@ void mem_init(void) ddr2_conf(&ddr2);
/* enable DDR2 clock */ - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* Chip select 1 is for DDR2/SDRAM */ csa = readl(&matrix->ebicsa); diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 0793e4a..7a01149 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -191,7 +191,7 @@ void mem_init(void)
/* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index d6e7e16..2bd436a 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -430,7 +430,7 @@ void mem_init(void)
/* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 71ec4b7..db45331 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -390,7 +390,7 @@ void mem_init(void)
/* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index de4291f..357b223 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -386,7 +386,7 @@ void mem_init(void)
/* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index d74743f..3294203 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -149,7 +149,7 @@ void mem_init(void) ddr2_conf(&ddr2);
/* enable DDR2 clock */ - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */ ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);