From: Thomas Diener dietho@gmx.de
Signed-off-by: Thomas Diener dietho@gmx.de --- arch/arm/include/asm/arch-mx25/iomux-mx25.h | 25 +++++++++++++++++++------ arch/arm/include/asm/imx-common/iomux-v3.h | 13 ++++++++++++- arch/arm/lib/asm-offsets.c | 9 +++++++++ 3 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h index 220cf4e..e403eb9 100644 --- a/arch/arm/include/asm/arch-mx25/iomux-mx25.h +++ b/arch/arm/include/asm/arch-mx25/iomux-mx25.h @@ -287,15 +287,19 @@ enum {
MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D6__CSPI3_SS0 = IOMUX_PAD(0x328, 0x130, 0x17, 0, 1, NO_PAD_CTRL),
MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D7__CSPI3_SS1 = IOMUX_PAD(0x32c, 0x134, 0x17, 0, 1, NO_PAD_CTRL),
MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D8__CSPI3_SS2 = IOMUX_PAD(0x330, 0x138, 0x17, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D9__CSPI3_SS3 = IOMUX_PAD(0x334, 0x13c, 0x17, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL), @@ -315,16 +319,18 @@ enum { MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0x568, 0, NO_PAD_CTRL), MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS0__LD16 = IOMUX_PAD(0x358, 0x160, 0x11, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS0__PWM2_PWMO = IOMUX_PAD(0x358, 0x160, 0x14, 0, 0, 0), MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
- MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0x564, 0, NO_PAD_CTRL), MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL), MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
@@ -341,6 +347,7 @@ enum { MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_UART1_RTS__GPT3_CAPIN1 = IOMUX_PAD(0x370, 0x178, 0x12, 0, 0, NO_PAD_CTRL), MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL), MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
@@ -356,6 +363,7 @@ enum {
MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL), MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL), + MX25_PAD_UART2_RTS__GPT1_CAPIN1 = IOMUX_PAD(0x380, 0x188, 0x13, 0x504, 2, NO_PAD_CTRL), MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL), @@ -385,17 +393,21 @@ enum { MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL), MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
- MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0x568, 1, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW0__UART3_RXD = IOMUX_PAD(0x3a0, 0x1a8, 0x01, 0, 0, NO_PAD_CTRL), MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW1__UART3_TXD = IOMUX_PAD(0x3a4, 0x1ac, 0x01, 0, 0, NO_PAD_CTRL), MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
- MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0x564, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW2__UART3_RTS = IOMUX_PAD(0x3a8, 0x1b0, 0x01, 0, 1, NO_PAD_CTRL), MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL), MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW3__UART3_CTS = IOMUX_PAD(0x3ac, 0x1b4, 0x01, 0, 0, NO_PAD_CTRL), MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL), MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
@@ -471,15 +483,15 @@ enum { MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL), + MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL), @@ -492,6 +504,7 @@ enum { MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL), MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL), MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_ACK__EPIT1_EPITO = IOMUX_PAD(0x40c, 0x218, 0x13, 0, 0, NO_PAD_CTRL), MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..d71d676 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -58,14 +58,18 @@ typedef u64 iomux_v3_cfg_t;
#define MUX_MODE_SHIFT 36 #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) +#define MUX_MODE_SION_SHIFT 40 +#define MUX_MODE_SION_MASK ((iomux_v3_cfg_t)0x1 << MUX_MODE_SION_SHIFT) #define MUX_PAD_CTRL_SHIFT 41 #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) #define MUX_SEL_INPUT_SHIFT 59 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ - MUX_MODE_SHIFT) + MUX_MODE_SHIFT) #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define MUX_SEL_INPUT(x) ((iomux_v3_cfg_t)(x) << MUX_SEL_INPUT_SHIFT) +
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ sel_input, pad_ctrl) \ @@ -79,6 +83,13 @@ typedef u64 iomux_v3_cfg_t; #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ MUX_PAD_CTRL(pad))
+#define NEW_SEL_INPUT(cfg, input) (((cfg) & ~MUX_SEL_INPUT_MASK) | \ + MUX_SEL_INPUT(input)) + +#define SET_MODE_SION(cfg) (((cfg) | MUX_MODE_SION_MASK)) + +#define CLEAR_MODE_SION(cfg) (((cfg) & ~MUX_MODE_SION_MASK)) + #define __NA_ 0x000 #define NO_MUX_I 0 #define NO_PAD_I 0 diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index b0c26e5..987cc8d 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -115,6 +115,15 @@ int main(void) /* AHB <-> IP-Bus Interface */ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + + /* M3IF */ + DEFINE(M3IF_CTL, offsetof(struct m3if_regs, ctl)); + + /* WEIM */ + DEFINE(WEIM_CSCR0U, offsetof(struct weim_regs, cscr0u)); + DEFINE(WEIM_CSCR0L, offsetof(struct weim_regs, cscr0l)); + DEFINE(WEIM_CSCR0A, offsetof(struct weim_regs, cscr0a)); + #endif
#if defined(CONFIG_MX27)