From: T Karthik Reddy t.karthik.reddy@xilinx.com
This patch adds support for nand multi chip select. Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number of nand chips.
Signed-off-by: Tummala Karthik Reddy t.karthik.reddy@xilinx.com Signed-off-by: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
drivers/mtd/nand/raw/Kconfig | 7 +++++++ drivers/mtd/nand/raw/arasan_nfc.c | 27 +++++++++++++-------------- 2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 008f7b4b4ba1..86e8b5e55d8a 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -243,6 +243,13 @@ config SYS_NAND_BUSWIDTH_16BIT not available while configuring controller. So a static CONFIG_NAND_xx is needed to know the device's bus-width in advance.
+config SYS_NAND_MAX_CHIPS + int "NAND max chips" + default 1 + depends on NAND_ARASAN + help + The maximum number of NAND chips per device to be supported. + if SPL
config SYS_NAND_U_BOOT_LOCATIONS diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index dc531ccb6822..2cd3f64dc63c 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -90,6 +90,8 @@ struct arasan_nand_command_format { #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000 +#define ARASAN_NAND_MEM_ADDR2_CS0_MASK (0x3 << 30) +#define ARASAN_NAND_MEM_ADDR2_CS1_MASK (0x1 << 30) #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
@@ -261,6 +263,16 @@ static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
static void arasan_nand_select_chip(struct mtd_info *mtd, int chip) { + u32 reg_val; + + reg_val = readl(&arasan_nand_base->memadr_reg2); + if (chip == 0) { + reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + } else if (chip == 1) { + reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; + writel(reg_val, &arasan_nand_base->memadr_reg2); + } }
static void arasan_nand_enable_ecc(void) @@ -713,9 +725,6 @@ static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); writel(reg_val, &arasan_nand_base->memadr_reg2); - reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2);
return 0; } @@ -804,9 +813,6 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); writel(reg_val, &arasan_nand_base->memadr_reg2); - reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
while (!(readl(&arasan_nand_base->intsts_reg) & @@ -859,10 +865,6 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1; writel(reg_val, &arasan_nand_base->pkt_reg);
- reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); while (!(readl(&arasan_nand_base->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { @@ -932,9 +934,6 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); writel(reg_val, &arasan_nand_base->memadr_reg2);
- reg_val = readl(&arasan_nand_base->memadr_reg2); - reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); buf_index = 0;
return 0; @@ -1219,7 +1218,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) writel(0x0, &arasan_nand_base->pgm_reg);
/* first scan to find the device and get the page size */ - if (nand_scan_ident(mtd, 1, NULL)) { + if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) { printf("%s: nand_scan_ident failed\n", __func__); goto fail; }