21 Sep
2008
21 Sep
'08
8:35 p.m.
Dear Victor,
in message 1221573553-1882-1-git-send-email-vgallardo@amcc.com you wrote:
...
- Use these scan options for PLB bus greater than or equal 200MHz
- else use the defaults. These options are known to return a cycle
- delay of T2 or better with a 200MHz PLB bus. Scanning the
- full list of WDTR/CLKTR should work, but currently it does not.
- HW team is investigating.
As you probably have noticed, I hesitate to pull the current patch into mainline, because it is still based on a temporary workaround.
Do you have any information when a clean solution for hte problem can be expected? I really would like to wait for the final patch.
What do you think?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
All your people must learn before you can reach for the stars.
-- Kirk, "The Gamesters of Triskelion", stardate 3259.2