On Thursday, August 27, 2015 at 07:14:07 AM, Chin Liang See wrote:
On Wed, 2015-08-26 at 15:58 +0200, marex@denx.de wrote:
On Wednesday, August 26, 2015 at 03:42:36 PM, Chin Liang See wrote:
On Wed, 2015-08-26 at 15:37 +0200, marex@denx.de wrote:
On Wednesday, August 26, 2015 at 03:13:15 PM, Chin Liang See wrote:
Hi,
[...]
> Yah, that is a nice enhancement in order to keep up with > controller enhancement. We definitely want to explore and > enable that at U-Boot in the future.
You mean you'll implement this functionality and then make your change to the QSPI driver to use it, in order to implement things properly ? :) In that case, I agree.
Sure, something I can look at in 1-2 months time.
Sure, no problem, that should be in time for the next merge window.
I still have laundry lists on ensuring the mainline SOCFPGA U-Boot has all the essential features as we have in github. Prior that happen, can I get an ACK from you? :)
No, sorry, you can not get ack on a patch which is hacky. You cannot push hacky code into mainline just for the sake of getting something somehow working, that's not how it works. We either do things proper or not at all.
In this case, probably its something we can work together on enabling the spi-nor?
Hi!
But the Cadence QSPI works in U-Boot, I'm using it on a board here.
Hi!
Yup, the basic function works. I am looking at 2 areas below
- Quad mode
Current driver is running at single IO mode. We yet to utilize the quad mode that is supported by the controller. Its for performance.
OK
- SCLK at 80MHz and beyond
The driver fail to work at higher SCLK frequency. The github version work well at 100MHz. I am troubleshooting on this now
Cool, thanks!
Best regards, Marek Vasut